US 5,479,372 AGranted

DRAM control circuit

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsFumiki Sato, Kouichi Fujita

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Abstract

A DRAM control circuit, having a second counter 12 which counts the number of times of generation of a refresh request signal generated by a first timer circuit 100, a set value register 13 which holds the maximum number of reservations for refreshing a DRAM 52, and a second comparator 14 which compares the count value of the counter 12 and a value held by the set value register 13, which cancels high-speed page mode and refreshes the DRAM 52 in a predetermined procedure only at a time when the second comparator 14 detects coincidence between the count value of the second counter 12 and a value held by the set value register 13. This configuration enables it to limit refreshing during high-speed page mode, while achieving a DRAM control circuit capable of operating in high-speed page mode more efficiently.

Claims2

Dependent claims

A control circuit for a DRAM, comprising:

a multiplexer which divides a time division multiplexed address signal outputted from a CPU into a row address signal and a column address signal;
timing means for generating a refresh request signal at a constant time interval;
a first register which holds the row address signal among the address signal outputted from said CPU;
first comparing means for comparing the row address signal among the address signal outputted from said CPU with the row address held by said first register;
signal generating means, which has storing means for storing the comparing result, coincidence/uncoincidence, by said first comparing means, and,
when said storing means stores the comparing result of disagreement by the first comparing means, for accessing to said DRAM by controlling said multiplexer according to the access request signal outputted from said CPU to output a row address signal and a valid row address strobe signal so that said DRAM recognizes the row address, and to output a column address signal and a valid column address strobe signal so that said DRAM recognizes the column address;
when said storing means stores the comparing result of coincidence by said first comparing means, for successively accessing to said DRAM by controlling said multiplexer according to the access request signal outputted from said CPU to supply column address signals and valid column address strobe signals successively to said DRAM so that said DRAM recognizes the column addresses;
and
when a refresh request signal is given from said timing means, for refreshing said DRAM by a predetermined procedure;
further comprising:
a counter which counts the number of times of generation of the refresh request signal generated by said timing means;
a second register which holds the maximum number of reservations for refreshing said DRAM;
and
second comparing means for comparing the count value of said counter and a value held by said second register;
wherein, when said storing means stores the comparing result of coincidence by said first comparing means, said signal generating means refreshes said DRAM by the predetermined procedure only at a time when said second comparing means detects coincidence between the count value of said counter and the value held by said second register.

12 more elements

A control circuit for a DRAM, comprising:

a multiplexer which divides a time division multiplexed address signal outputted from a CPU into a row address signal and a column address signal, according to a signal supplied in accordance to the configuration of a DRAM;
timing means for generating a refresh request signal at a constant time interval;
a first register which holds the row address signal among the address signal outputted from said CPU;
first comparing means for comparing only the row address signal among the address signal outputted from said CPU with a row address held by said first register, according to the signal supplied in accordance to the configuration of said DRAM;
signal generating means, which has storing means for storing the comparing result, coincidence/uncoincidence, by said first comparing means, and,
when said storing means stores the comparing result of disagreement by said first comparing means, for accessing to said DRAM by controlling said multiplexer according to the access request signal outputted from said CPU to output a row address signal and a valid row address strobe signal so that said DRAM recognizes the row address, and to output a column address signal and a valid column address strobe signal so that said DRAM recognizes the column address;
when said storing means stores the comparing result of coincidence by said first comparing means, for successively accessing to said DRAM by controlling said multiplexer according to the access request signal outputted from said CPU to supply column address signals and valid column address strobe signals successively to said DRAM so that said DRAM recognizes the column addresses;
and
when a refresh request signal is given from said timing means, for refreshing said DRAM by a predetermined procedure;
further comprising:
a counter which counts the number of times of generation of the refresh request signal generated by said timing means;
a second register which holds the maximum number of reservations for refreshing said DRAM;
and
second comparing means for comparing the count value of the counter and a value held by said second register;
wherein, when said storing means stores the comparing result of coincidence by said first comparing means, said signal generating means refreshes said DRAM by the predetermined procedure only at a time when said second comparing means detects coincidence between the count value of said counter and the value held by said second register.

12 more elements

Dependencies are inferred from the claim text.