Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of blocks in which memory cells are respectively arranged on a plurality of normal columns and one spare column,
• a plurality of normal column selection lines respectively provided for selecting any one of said normal columns, within said respective blocks;
• one spare column selection line respectively provided for selecting instead said spare column in the case where any one of said normal columns is defective, within said respective blocks;
• non-selection means provided every said normal column selection lines, and adapted so that when a corresponding normal column is defective, said non-selection means allows that normal column selection line to be brought into non-selective state, and
• selector means adapted so that when said normal columns within a corresponding block are all in non-selective state within said respective blocks, said selector means allow said spare column selection line to be brought into selective state.

A semiconductor memory device, comprising:

• a plurality of normal row selection lines having memory cells respectively arranged thereon;
• a spare row selection line having spare memory cells arranged thereon;
• a plurality of row selection units for selecting one of the normal row selection lines and outputting a second potential to the selected one of the normal row selection lines;
• a plurality of fuses connected respectively between the normal row selection lines and outputs of the row selection units;
• a plurality of first circuits provided respectively at the normal row selection lines which set the respective normal selection lines at a first potential except in the case that the corresponding normal selection line is selected and the corresponding fuse is not blown off;
• a plurality of detecting circuits provided respectively at the normal row selection lines for detecting the respective levels of the normal selection lines;
• and
• a judging circuit connected to outputs of the detecting circuits which selects the spare row selection line when all the detecting circuits detect the levels of the respective normal row selection lines to be at the first potential.

A semiconductor memory device, comprising:

• a plurality of normal column selection lines in which memory cells are respectively arranged thereon;
• a spare column selection line in which spare memory cells are arranged thereon;
• a plurality of column selection units for selecting one of the normal column selection lines and outputting a second potential to the selected one of the normal column selection lines;
• a plurality of fuses connected respectively between the normal column selection lines and outputs of the column selection units;
• a plurality of first circuits provided respectively at the normal column selection lines which set the respective normal column selection lines at a first potential except when the corresponding normal column selection line is selected and the corresponding fuse is not blown off;
• a plurality of detecting circuits provided respectively at the normal column selection lines for detecting the respective levels of the normal column selection lines;
• and
• a judging circuit connected to outputs of the detecting circuits which selects the spare column selection line when all the detecting circuits detect that the levels of the respective normal column lines are at the first potential.