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US 5,479,370 AGranted
Semiconductor memory with bypass circuit
AssigneeKabushiki Kaisha Toshiba
InventorsTohru Furuyama, Donald C. Stark
Life of this patent
Estimating the term…
Abstract
A semiconductor memory of this invention comprises a memory cell array containing memory cells arranged in matrix form, word lines each connected to all the memory cells in the same row, and bit lines each connected to all the memory cells in the same column, a shift register containing a plurality of stages of shift circuits which is used as a serial address pointer for serially specifying the addresses of actually used rows and/or columns in the memory cell array, a bypass circuit capable of forming a bypass for the shift circuit at a given stage of the shift register, and a bypass control circuit for determining whether or not a bypass is to be formed by the bypass circuit.
Claims27
A semiconductor memory comprising:
- a memory cell array containing memory cells arranged in a row and column matrix, word lines each connected to the memory cells in the same row, and bit lines each connected to the memory cells in the same column;
- a first serial address pointer comprising a first shift register containing a plurality of shift circuits, wherein enabled ones of said plurality of shift circuits in said first shift register determine the rows actually used in the memory cell array;
- a second serial address pointer comprising a second shift register containing a plurality of shift circuits, wherein enabled ones of said plurality of shift circuits in said second shift register determine the columns actually used in the memory cell array;
- a first bypass circuit provided for the first shift register capable of disabling given ones of said plurality of shift circuits in said first shift register;
- a second bypass circuit provided for the second shift register capable of disabling given ones of said plurality of shift circuits in said second shift register;
- a first bypass control circuit for determining whether said first bypass circuit disables one or more of said given ones of said plurality of shift circuits in said first shift register;
- and
- a second bypass control circuit for determining whether Or not said second bypass circuit disables one or more of said given ones of said plurality of shift circuits in said second shift register.
5 more elements
A semiconductor memory comprising:
- a memory cell array containing memory cells arranged in a row and column matrix, word lines each connected to the memory cells in the same row, and bit lines each connected to the memory cells in the same column;
- a line buffer which contains as many stages of buffer circuits as the number of memory cells in a column or a row in the memory cell array and which is used to exchange a column or a row of memory cell data with the memory cell array;
- a serial address pointer for serially specifying the buffer circuit at an enabled stage of the line buffer, wherein said serial address pointer contains
- a shift register with multiple stages of shift circuits,
- a bypass circuit capable of disabling given ones of said multiple stages of shift circuits in said shift register;
- and
- a bypass control circuit for determining whether or not said bypass circuit disables one or more of said given ones of said multiple stages of shift circuits.
4 more elements
A semiconductor memory with a plurality of ports for video signals comprising:
- a memory cell array arranged in rows and columns;
- a data register which contains multiple stages of register circuits for exchanging data in parallel with the memory cell array and which serially exchanges data with an external circuit via a serial port;
- a serial address pointer for serially specifying the buffer circuit at an enabled stage of the line buffer, wherein said serial address pointer contains
- a shift register with multiple stages of shift circuits,
- a bypass circuit capable of disabling given ones of said multiple stages of shift circuits in said shift register;
- and
- a bypass control circuit for determining whether or not said bypass circuit disables one or more of said given ones of said multiple stages of shift circuits.
4 more elements
A semiconductor memory comprising:
- a memory cell array containing memory cells connected to word lines and bit lines and arranged in rows and columns, wherein each of the memory cells is capable of storing a plurality of bits of information and includes
- a plurality of MOS transistors connected in series between first and second nodes wherein said first and second nodes are connected to each another and to one of said bit lines, each of said MOS transistors having a gate connected to one of said word lines;
- a plurality of data storage capacitors each connected to a respective corresponding connection node between said series-connected MOS transistors;
- a serial address pointer comprising a shift register containing a plurality of shift circuits, wherein said shift register contains as many shift circuits as 1/k (k is an integer) of the number of rows of said memory cell array and enabled ones of said plurality of shift circuits determine the rows and columns actually used in said memory cell array;
- a bypass circuit capable of disabling given ones of said plurality of shift circuits in said shift register;
- and
- a bypass control circuit for determining whether or not said bypass circuit disables one or more of said given ones of said plurality of shift circuits;
- a word-line driving circuit for selectively driving said word lines;
- a column select circuit for selecting a column of said memory cell array;
- a column address-specifying circuit for performing select control of said column select circuit, wherein
- said shift register specifies a row address for selectively driving said word lines,
- said bypass circuit and said bypass control circuit are provided for each shift circuit of said shift register, and
- the output of each shift circuit of said shift register is used to perform selection control of said word-line driving circuits in units of k circuits.
10 more elements
A semiconductor memory comprising:
- a memory cell array containing memory cells connected to word lines and bit lines and arranged in rows and columns, wherein given ones of said rows or columns are redundant rows or columns and each of the memory cells is capable of storing a plurality of bits of information and includes
- a plurality of MOS transistors connected in series between first and second nodes wherein said first and second nodes are connected to each another and to one of said bit lines, each of said MOS transistors having a gate connected to one of said word lines;
- a plurality of data storage capacitors each connected to a respective corresponding connection node between said series-connected MOS transistors;
- a serial address pointer comprising a shift register containing a plurality of shift circuits, wherein said shift register contains as many shift circuits as 1/k (k is an integer) of the number of rows of said memory cell array and enabled ones of said plurality of shift circuits determine the rows and columns actually used in said memory cell array;
- a bypass circuit capable of disabling given ones of said plurality of shift circuits in said shift register;
- and
- a bypass control circuit for determining whether or not said bypass circuit disables one or more of said given ones of said plurality of shift circuits;
- a word-line driving circuit for selectively driving said word lines;
- a column select circuit for selecting a column of said memory cell array;
- a column address-specifying circuit for performing select control of said column select circuit, wherein
- said shift register specifies a row address for selectively driving said word lines,
- said bypass circuit and said bypass control circuit are provided for each shift circuit of said shift register, and
- the output of each shift circuit of said shift register is used to perform selection control of said word-line driving circuits in units of k circuits.
10 more elements
Dependencies are inferred from the claim text.