Semiconductor integrated circuit device and semiconductor memory device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTetsuya Matsumura, Satoshi Kumaki, Shinichi Nakagawa
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Abstract
In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.
Claims3
A semiconductor memory device including a data storage node and a data reading node, comprising:
- write data transfer means responsive to a write control signal for transferring externally applied write data to said data storage node;
- first and second switching means each including a control electrode, one electrode and the other electrode, and responsive to the write data transferred by said write data transfer means for being turned on/off in a complementary manner;
- an inverter having its input node connected together with the one electrodes of said first and second switching means to the data reading node, and its output node connected together with the control electrodes of said first and second switching means to said data storage node;
- a set/reset terminal for setting/resetting a data latch function to the other electrode of said first or second switching means, and
- read data transfer means responsive to a read control signal for externally transferring read data from said data reading node.
Dependencies are inferred from the claim text.