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AssigneeThe Regents of the University of California
InventorsAlan N. Willson, Jr., Kei Y. Khoo, Alan Kwentus
Estimating the term…
A novel switchable unit-delay has been developed for the efficient implementation of programmable digital finite impulse response filters and correlators. A p-tap consisting of this novel switchable unit-delay and a two-non-zero-digit partial product generator and adder have been implemented. The combination of several p-taps, made possible by the switchable unit-delay, allows for the efficient implementation of coefficients with more than two non-zero digits. In a straightforward implementation of a programmable finite impulse response filter, many tap "multipliers" would significantly waste valuable computational resources since all filter taps would need to accommodate "difficult" coefficient values (i.e., many non-zero digits), while for any specific transfer function, most filter taps would not require such extreme capabilities. The switchable unit-delay not only allows the programing of the number of taps and the specific tap-coefficient values, it provides the capability for programing the optimal allocation of hardware resources to each filter tap.
A first digital filter tap element having a first predetermined number of digits for part of a filter having a plurality of such tap elements for digitally filtering an input digital signal according to an algorithm based upon a first filter coefficient having a second predetermined number of digits, the first tap element comprising:
A computational element in a filter having a plurality of such elements for performing a computation on an input with a coefficient of not greater than a predetermined precision comprised of:
A method for digitally filtering a digital input signal with a digital filter algorithm having coefficients, each coefficient having a predetermined number of digits, the method comprising:
Dependencies are inferred from the claim text.