Vehicle diagnosis system

A vehicle diagnostic system comprising:

• storage means for detecting various abnormalities of a vehicle and for storing abnormality information;
• abnormality information erasing means for erasing abnormality information stored in said storage means in response to an erase signal from diagnosis means;
• erase condition detecting means for detecting whether the abnormality information is being erased;
• erase status detecting means for detecting whether erasure of abnormality information is in execution by said abnormality information erasing means and for preventing erroneous output of pre-erasure abnormality information from said storage means when a read command is input externally during erasure of abnormality information from said storage means;
• and
• abnormality information output means for outputting abnormality information after erasure, when said erase status detecting means detects that erasure of abnormality information is in execution, in response to a read signal applied from said diagnosis means, and for outputting abnormality information stored in said storage means when said erase status detecting means detects that erasure of abnormality information is not in execution.

A vehicle diagnostic system comprising:

• a plurality of CPUs including other CPUs and a main CPU which controls vehicle operation, detects various abnormalities and conducts information communication with an external device;
• a plurality of storage devices provided in said plurality of CPUs for storing abnormality information detected by the individual ones of the plurality of CPUs, wherein said main CPU includes:
• erase instruction output means for outputting an abnormality information erase instruction to the other CPUs in response to an erase signal from said external device;
• erase instruction output means for outputting an abnormality information erase instruction to the other CPUs when no erase signal from said external device is received, and for outputting predetermined data to the other CPUs when an erase signal has been received;
• erase status detecting means for detecting whether an erase signal has been received.

A vehicle diagnostic system comprising:

• a controller including a plurality of control means, each of said control means having a CPU for control of vehicle operation on the basis of vehicle information and a RAM storing control information, said control means being connected so as to permit transmission and receiving of data through direct memory access;
• and
• a diagnostic unit connectable to said controller and including:
• read requesting means for requesting the reading of control information stored at a desired address of said RAM;
• read request address writing means for writing said desired address corresponding to said read request of control information from said read requesting means into a first direct memory access region;
• read information writing means for writing control information and an address value corresponding to said desired address written in said first direct memory access region into a second direct memory access region;
• and
• responding means for sending control information written in said second direct memory access region to said diagnostic unit as a response when there is agreement between the address value in said second direct memory access region and said desired address value and upon lapse of a prescribed period of time after the agreement.

A vehicle diagnostic system comprising:

• a main CPU having a RAM for storing information, said main CPU performing data communication with an external diagnosis unit, and
• at least one other CPU having a RAM for storing control information, said at least one other CPU calculating an amount of vehicle control in accordance with a prescribed control program, wherein said main CPU includes:
• instruction signal receiving means for receiving an instruction signal for reading out desired control information in the control information stored in the RAM of said at least one other CPU;
• read requesting means for causing a first storage area of said at least one other CPU to store a requested address corresponding to said desired control information in response to the request of said instruction signal;
• a second storage area for storing said requested address responded by said at least one other CPU;
• a third storage area for storing requested address data corresponding to the requested address responded by said at least one other;
• response completion detecting means for detecting a completion of response signal from the at least one other CPU in response to agreement between the value stored in the second storage area and said requested address;
• and
• desired control information transmitting means for transmitting the requested address data stored in said third storage area to said external diagnosis unit in response to detection of said completion of response signal, and for transmitting predetermined data to prevent erroneous output to said external diagnosis unit when no completion of response signal is detected by said response completion detecting means;
• wherein each said at least one other CPU includes:
• requested address data reading means for reading out the requested address data corresponding to said requested address stored in said first storage area from said RAM;
• and
• desired control information responding means for causing said third storage area to store said requested address data and then for causing said second storage area to store said address.