Huffman decoding method, circuit and system employing conditional subtraction for conversion of negative numbers

A data processing apparatus for decoding a continuous stream of Huffman encoded data, each datum having a size portion of a predetermined number of bits and a value portion of a variable number of bits, said data processing apparatus comprising:

• a set of a plurality of data registers, a data size stored in a first data register and a value stored in a second data register;
• an expand circuit having an input connected to said set of data registers and an output, said expand circuit generating at said output a multibit digital number having a number of right justified "1's" corresponding to the signal at said input;
• an arithmetic logic unit having first and second inputs connected to said set of data registers, a function input and an output, said arithmetic logic unit forming a combination of input signals received at said first and second inputs at said output, said combination corresponding to a function signal received at said function input, said arithmetic logic unit having a status detector generating a single bit status signal indicating whether said output is zero;
• a status register connected to said status detector for storing said single bit status signal;
• and
• an instruction decoder responsive to a stream of instructions connected to said set of data registers, said expand circuit, said barrel rotator and said arithmetic logic unit, said instruction decoder responsive to a first instruction to
• supply data in said second data register to said first input of said arithmetic logic unit,
• supply data stored in said first data register to said input of said expand circuit,
• supply said output of said expand circuit to said second input of said arithmetic logic unit,
• control said arithmetic logic unit to subtract of data received at said second input from data received at said first input, and
• store said output of said arithmetic logic unit in said second data register only if said single bit status signal stored in said status register indicates a zero output of said arithmetic logic unit.

An data processing system for decoding a continuous stream of Huffman encoded data, each datum having a size portion of a predetermined number of bits and a value portion of a variable number of bits, said data processing system comprising:

• an data system bus transferring data and addresses;
• a system memory connected to said data system bus, said system memory storing data and transferring data via said data system bus;
• an data processor circuit connected to said data system bus, said data processor circuit including
• a set of a plurality of data registers, a data size stored in a first data register and a value stored in a second data register,
• an expand circuit having an input connected to said set of data registers and an output, said expand circuit generating at said output a multibit digital number having a number of right justified "1's" corresponding to the signal at said input,
• an arithmetic logic unit having first and second inputs connected to said set of data registers, a function input and an output, said arithmetic logic unit forming a combination of input signals received at said first and second inputs at said output, said combination corresponding to a function signal received at said function input, said arithmetic logic unit having a status detector generating a single bit status signal indicating whether said output is zero,
• a status register connected to said status detector for storing said single bit status signal, and
• an instruction decoder responsive to a stream of instructions connected to said set of data registers, said expand circuit, said barrel rotator and said arithmetic logic unit, said instruction decoder responsive to a first instruction to
• supply data in said second data register to said first input of said arithmetic logic unit,
• supply data stored in said first data register to said input of said expand circuit,
• supply said output of said expand circuit to said second input of said arithmetic logic unit,
• control said arithmetic logic unit to subtract of data received at said second input from data received at said first input, and
• store said output of said arithmetic logic unit in said second data register only if said single bit status signal stored in said status register indicates a zero output of said arithmetic logic unit.