Noise and glitch suppressing filter with feedback

A filter circuit comprising:

• an input node for receiving an unfiltered input signal;
• an output node for providing a filtered output signal;
• an intermediate node;
• an integrator having an input coupled to the input node and an output coupled to the intermediate node;
• a signal conditioning circuit having an input coupled to the intermediate node and an output coupled to the output node;
• and
• means for forcing the intermediate node to a first voltage if the input node and the output node are each at a first logic state, and for forcing forcing the intermediate node to a second voltage if the input node and the output node are each at a second logic state having two parallel circuit portions, wherein each parallel circuit portion includes a first input coupled to the input node, a second input coupled to the output node, and an output coupled to the intermediate node, and wherein one of the parallel circuit portions includes;
• a NAND gate having two inputs and an output, wherein the two inputs of the NAND gate form the first and second inputs of the parallel circuit portion;
• and
• a P-channel transistor having a gate coupled to the output of the NAND gate, a source coupled to a source of supply voltage, and a drain forming the output of the parallel circuit portion.

A filter circuit comprising:

• an input node for receiving an unfiltered input signal;
• an output node for providing a filtered output signal;
• an intermediate node;
• an integrator having an input coupled to the input node and an output coupled to the intermediate node;
• a Schmitt trigger having an input coupled to the intermediate node and an output coupled to the output node;
• and
• a reset circuit having two parallel circuit portions, wherein each parallel circuit portion includes a first input coupled to the input node, a second input coupled to the output node, and an output coupled to the intermediate node, wherein one of the parallel circuit portions includes:
• a NOR gate having two inputs and an output, wherein the two inputs of the NOR gate form the first and second inputs of the parallel circuit portion;
• and
• an N-channel transistor having a gate coupled to the output of the NOR gate, a source coupled to ground, and a drain forming the output of the parallel circuit portion.

A filter circuit comprising:

• an input node for receiving an unfiltered input signal;
• an output node for providing a filtered output signal;
• an intermediate node;
• an integrator having an input coupled to the input node and an output coupled to the intermediate node;
• a signal conditioning circuit having an input coupled to the intermediate node and an output coupled to the output node;
• and
• means for forcing the intermediate node to a first voltage if the input node and the output node are each at a first logic state, and for forcing forcing the intermediate node to a second voltage if the input node and the output node are each at a second logic state having two parallel circuit portions, wherein each parallel circuit portion includes a first input coupled to the input node, a second input coupled to the output node, and an output coupled to the intermediate node, and wherein one of the parallel circuit portions includes:
• a NOR gate having two inputs and an output, wherein the two inputs of the NOR gate form the first and second inputs of the parallel circuit portion;
• and
• an N-channel transistor having a gate coupled to the output of the NOR gate, a source coupled to ground, and a drain forming the output of the parallel circuit portion.