US 5,479,130 A · Auto-zero switched-capacitor integrator

Abstract

A switched-capacitor auto-zero integrator includes and integrator circuit and a correction circuit. The integrator circuit may be any circuit including an operational amplifier having an input line and an output line, an input capacitor coupled to be charged by an Input voltage, an integrating capacitor coupled to the output line, and at least one integrating switch operable during an integrating time interval to connect the input capacitor to the integrating capacitor such that the integrating capacitor is charged to compensate for charge of the input capacitor. The correction circuit includes an offset capacitor coupled to the input line and at least one correction switch operable in an auto-zero sub-interval: and a correction sub-interval. The sub-intervals occur only during the integrating interval such that the offset capacitor is charged by an offset voltage and a gain error voltage of the operational amplifier during the auto-zero sub-interval and the offset capacitor is connected to a summing node between the input capacitor and the integrating capacitor during the correction sub-interval.

Claims16

Dependent claims

A switched-capacitor auto-zero integrator comprising:

an integrator circuit including an operational amplifier having an input line and an output line, an input capacitor coupled to be charged at selected times by an input voltage, an integrating capacitor coupled to the output line, and at least one integrating switch operable during an integration time interval to connect the input capacitor to the integrating capacitor such that the integrating capacitor is charged to compensate for charge on the input capacitor;
and
a correction circuit including an offset capacitor coupled to the input line and at least one correction switch operable in an auto-zero time sub-interval and a correction time sub-interval, the time sub-intervals occurring only during the integration interval, to connect the offset capacitor such that the offset capacitor is charged by an offset voltage and a gain error voltage or the operational amplifier during the auto-zero time sub-interval and to connect the offset capacitor to a summing node between the input capacitor and the integrating capacitor during the correction sub-interval.

A switched-capacitor auto-zero integrator comprising:

an integrator circuit including an input line for receiving an input voltage, an operational amplifier having an input and an output, a plurality of integrating switches operable in first and second time intervals, an input capacitor connected to the input line through at least one of the integrating switches such that the input capacitor is charged by the input voltage during at least one of the first and second time intervals, and an integrating capacitor connected to the output of the operational amplifier and to the input capacitor through at least another of the integrating switches such that the integrating capacitor is charged to compensate for charge on the input capacitor during an integrating time interval, the integrating time interval including at least one of the first and second time intervals;
and
a correction circuit coupled between said input line and said input capacitor including an offset capacitor and plurality of correction switches operable in an auto-zero time sub-interval and a correction time sub-interval, wherein the time sub-intervals occur only during the integrating interval, to connect the offset capacitor such that the offset capacitor is charged by an offset voltage and a gain error voltage of the operational amplifier during the auto-zero time sub-interval and to connect the offset capacitor to a summing node between the input capacitor and the integrating capacitor during the correction time sub-interval.

Dependencies are inferred from the claim text.

Auto-zero switched-capacitor integrator

Life of this patent

Auto-zero switched-capacitor integrator

Life of this patent

Abstract

Claims16