Single ram multiple-delay variable delay circuit

A multi-input variable delay circuit, for delaying one or more blocks of input data by respective variable delays aggregating up to X delay increments, comprising:

• a memory array comprising a plurality of storage locations, including locations 1 through X;
• a clock coupled to said memory array, wherein said clock determines a duration of one or more delay increments of said one or more blocks;
• an access circuit, coupled to said memory array, which writes input data blocks into said memory array and reads data blocks out of said memory array;
• a first delay control circuit, coupled to said memory array and to said clock, which enables a first input data block to be delayed by a first variable delay equal to Y delay increments, by causing said access circuit to write said first input data block into a first portion of said memory array, and to read said first input data block out of said first portion of said memory array wherein said first portion of said memory array comprises only Y storage locations of said memory array, where Y does not exceed X;
• and
• a second delay control circuit, coupled to said memory array and to said clock and responsive to a signal indicative of the value Y, which enables a second input data block to be delayed by a second variable delay, by causing said access circuit to write said second input data block into a second portion of said memory array, and read said second input data block out of said second portion of said memory array, wherein said second portion of said memory array comprises a total number of said storage locations Y', wherein said Y' storage locations do not exceed X-Y storage locations, and wherein said Y' storage locations are storage locations other than said Y storage locations utilized by said first delay control circuit.

A multi-input variable delay circuit, for delaying one or more blocks of input data by are respective variable delays aggregating up to X delay increments, comprising:

• a memory array for storing blocks of input data at a plurality of storage locations, including locations 1 through X;
• a clock coupled to said memory array, wherein said clock determines a duration of one or more delay increments of said one or more blocks;
• an access circuit, coupled to said memory array, which writes input data blocks into said memory array and reads data blocks out of said memory array:
• a first delay control circuit, coupled to said memory array and to said clock, which enables a first input data block to be delayed by a first variable delay equal to Y delay increments, by causing said access circuit to write said first input data block into a first portion of said memory, and to read said first input data block out of said first portion, wherein said first portion comprises Y storage locations of said memory array, where Y does not exceed X;
• and
• a second delay control circuit, coupled to said memory array and to said clock and responsive to a signal indicative of the value Y, which enables a second input data block to be delayed by a second variable delay, by causing said access circuit to write said second input data block into a second portion of said memory array, and read said second input data block out of said second portion of said memory array, wherein said second portion of said memory array comprises a total number of said storage. locations Y', wherein said Y' storage locations do not exceed X-Y storage locations, and wherein said Y' storage locations are storage locations other than said Y storage locations utilized by said first delay control circuit, and wherein said second delay control circuit includes a comparator arranged for monitoring said storage locations utilized by said first delay control circuit.

A multi-input variable delay circuit, for delaying one or more blocks of input data by respective variable delays aggregating up to X delay increments, comprising:

• a memory array comprising X storage locations 1 through X;
• a clock coupled to said memory array, wherein said clock determines a duration of one or more delay increments of said one or more blocks of input data;
• an access circuit, coupled to said memory array, which writes input data blocks into said memory array and reads data blocks out of said memory array;
• a first delay control circuit, coupled to said memory array and to said clock, which enables a first input data block to be delayed by a first variable delay equal to Y delay increments, by causing said access circuit to write said first input data block into a first portion of said memory array, and to read said first input data block out of said first portion of said memory array, wherein said first portion of said memory array comprises only Y storage locations 1 through Y of said X storage locations of said memory array, where Y does not exceed X;
• and
• a second delay control circuit, coupled to said memory array and to said clock, which enables a second input data block to be delayed by a second variable delay equal to a number of delay increments not exceeding X-Y, by causing said access circuit to write said second input data block into a second portion of said memory array, and to read said second input data block out of said second portion of said memory array, wherein said second portion of said memory array comprises some or all of X-Y storage locations Y+1 through X of said X storage locations of said memory array, wherein said second delay control circuits receives a signal indicative of the value Y, and wherein said second delay control circuit includes a comparator for controlling operation of said second delay control circuit to cause said input block to be written into storage locations other than said Y storage locations utilized by said first delay control circuit.