Slew rate controller for high speed bus
AssigneeNexgen Microsystems
InventorsPhilip Y. Pun, William A. Stutz
Life of this patent
Estimating the term…
Abstract
A technique for high speed transmission of digital signals on a bus line with reduced signal ringing, bounce and bus contention current. The approach uses a multi-partitioned driver design with temporary and steady state parts incorporating internal feedback and delay techniques to control the output slew rate. A built-in function outputs the driving status of the transceiver and allows the output to enter the high impedance status asynchronously.
Claims6
In an integrated circuit, an apparatus for transmitting and receiving digital signals through a connector for connection with a signal line comprising:
- a first driver circuit coupled to said connector capable of providing sink or source current to move a voltage level on said signal line to a desired voltage when said connector is connected to said signal line;
- a second driver circuit coupled to said connector capable of providing sink or source current to maintain a desired voltage level on said signal line when said connector is connected to said signal line;
- an input latch coupled to said connector capable of latching data in response to a timing signal;
- and
- timing circuitry coupled to said first driver circuit, said second driver circuit, and said input latch for independently turning-on and turning-off said first and said second driver circuits, and for controlling said input latch.
A method for transmitting data between a plurality of data processing circuits on a signal line comprising:
- enabling one of said data processing circuits to transmit data during the first part of a data clock cycle with a first driver circuit coupled to said signal line capable of providing sink or source current to move a voltage level on said signal line to a desired voltage;
- enabling said one of said data processing circuits to transmit data during the first and second parts of a data cycle with a second driver circuit coupled to said signal line capable of maintaining a desired voltage level on said signal line;
- latching the data at each of said data processing circuits with an input latch coupled to said signal line at the end of said data cycle.
An apparatus for communicating digital signals on a signal line between a transmitting data processing circuit and a receiving data processing circuit comprising:
- a first driver circuit operatively connected to said transmitting data processing circuit and coupled to said signal line capable of providing sink or source current to move a voltage level on said signal line to a desired voltage;
- a second driver circuit operatively connected to said transmitting data processing circuit and coupled to said signal line capable of providing sink or source current to maintain a desired voltage level on said signal line;
- an input latch operatively connected to said receiving data processing circuit and coupled to said signal line capable of latching data on said signal line in response to a timing signal;
- and
- timing circuitry coupled to said first driver circuit, said second driver circuit, and said input latch for controlling said latch and for turning-on and turning-off of said first and said second driver circuits.
Dependencies are inferred from the claim text.