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US 5,479,118 AGranted
Pulse width discriminating circuit
AssigneeNEC Corporation
InventorShinji Niijima
Life of this patent
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AssigneeNEC Corporation
InventorShinji Niijima
Estimating the term…
A pulse width discriminating circuit comprises an edge detecting circuit receiving an input signal for generating a detection signal when the input signal rises up, first to third counters each cleared by the detection signal and counting a different count clock, a capture register responding to the detection signal to store a count value of the first counter, an arithmetic operation circuit for multiplying the stored value in the capture register with a predetermined constant number, and a compare register storing the result of the multiplication operation performed in the arithmetic operation circuit. First to third comparators are provided each comparing the stored value of the compare register with a count value of a corresponding one counter of the first to third counters for generating a coincidence signal, and each of a plurality of latch circuits responds to the coincidence signal of a corresponding comparator of the first to third comparators to latch a level of the input signal.
A pulse width discriminating circuit comprising an edge detecting circuit receiving an input signal for generating a detection signal when said input signal changes from a first level to a second level, a plurality of counters each cleared by said detection signal and counting a different count clock, a capture register responding to said detection signal to store a count value of one counter of said plurality of counters, an arithmetic operation circuit for executing a predetermined arithmetic operation on the stored value in said capture register, a compare register storing the result of said predetermined arithmetic operation performed in said arithmetic operation circuit, a plurality of comparators each comparing the stored value of said compare register with a count value of a corresponding one counter of said plurality of counters for generating a coincidence signal, a plurality of latch circuits each responding to said coincidence signal of a corresponding comparator of said plurality of comparators to latch a level of said input signal.
A pulse width discriminating circuit comprising an edge detecting circuit receiving an input signal for generating a detection signal when said input signal changes from a first level to a second level, a counter cleared by said detection signal and counting a count clock, a capture register responding to said detection signal to store a count value of said counter, an arithmetic operation circuit for executing a plurality of predetermined arithmetic operations on the stored value in said capture register, a plurality of compare registers each storing the result of a corresponding one of said predetermined arithmetic operations performed in said arithmetic operation circuit, a plurality of comparators each comparing the stored value of a corresponding one compare register of said plurality of compare registers with the count value of said counter for generating a coincidence signal, a plurality of latch circuits each responding to said coincidence signal of a corresponding comparator of said plurality of comparators to latch a level of said input signal.
Dependencies are inferred from the claim text.