Level conversion circuits for converting a digital input signal varying between first and second voltage levels to a digital output signal varying between first and third voltage levels

A level conversion circuit for converting a digital input signal varying between a first (VSS) voltage level and a second (VDD1) voltage level to a digital output signal varying between said first voltage level (VSS) and a third voltage level (VDD2), said level conversion circuit comprising:

• a series circuit coupled between first (VDD2) and second (VSS) poles of a DC supply source, said series circuit including a series connection of main paths of a first transistor (N2) and of a second transistor (N1), a control electrode of the second transistor (N1) being connected to receive said digital input signal:
• a load impedance (P2, P3, N3) coupled between said first DC supply source pole (VDD2) and an output terminal (OUT) of said level conversion circuit, said load impedance being connected to said series connection of main paths of the first and second transistors (N2, N1);
• wherein said second transistor (N1) is of a same first conductivity type as said first transistor (N2);
• a third transistor (P1) having a main path which is connected in parallel to said second transistor (N1), said third transistor (P1) being of a second conductivity type opposite to said first conductivity type, and said third transistor (P1) having a control electrode;
• and
• a control electrode of said first transistor (N2) and said control electrode of said third transistor (P1) being biased by respective constant DC bias voltages (VBIAS1A, VBIAS1B).