US 5,479,115 A · Signal processing device and level converter circuit

Abstract

There is disclosed a signal processing device which includes a pre-processing circuit (31) for performing a serial-to-parallel conversion on an intermediate signal (M.sub.2) at a PECL level, the serial-to-parallel conversion at the PECL level being permitted to deal with a high frequency, and a level converter circuit (12) for performing a conversion from the ECL to PECL levels both having the same logic level width, which conversion consumes less power than a conversion between the ECL and CMOS levels having different logic level widths. The level conversion of a parallel signal requires less power consumed than a level conversion of a serial signal. The signal processing device further includes a level converter circuit (13) for performing a conversion into the CMOS level after obtaining an intermediate signal (M.sub.3) which is a parallel signal. An intermediate signal (M.sub.4) is at the CMOS level and has a low frequency. The signal processing device which operates at the CMOS level processes the high-frequency signal at the ECL level for reduction in consumed power.

Claims16

Dependent claims

A signal processing device receiving a first input signal having a TTL level and a second input signal having an ECL level for performing signal processing at a CMOS level to provide a first output signal having the TTL level and a second output signal having the ECL level, said signal processing device comprising:

(a) a first level converter circuits for level converting said first input signal into a first intermediate signal at the CMOS level;
(b) a second level converter circuit for level converting said second input signal into a second intermediate signal at a pseudo-ECL level;
(c) a pre-processing circuit for serial-to-parallel converting said second intermediate signal to produce a third intermediate signal at the pseudo-ECL level;
(d) a third level converter circuit for level converting said third intermediate signal into a fourth intermediate signal at the CMOS level;
(e) a signal processing circuit for performing predetermined signal processing on said first intermediate signal and said fourth intermediate signal to produce a fifth intermediate signal and a sixth intermediate signal both at the CMOS level in respective corresponding relation to said first and fourth intermediate signals;
(f) a fourth level converter circuit for level converting said fifth intermediate signal into said first output signal;
(g) a fifth level converter circuit for level converting said sixth intermediate signal into a seventh intermediate signal at the pseudo-ECL level;
(h) a post-processing circuit for parallel-to-serial converting said seventh intermediate signal to produce an eighth intermediate signal at the pseudo-ECL level;
and
(i) a sixth level converter circuit for level converting said eighth intermediate signal into said second output signal.

7 more elements

A level converter circuit for converting a first signal at an ECL level into a second signal at a pseudo ECL level, said level converter circuit comprising:

(a) first, second, and third power supplies for providing a first potential, a second potential lower than said first potential, and a third potential lower than said second potential, respectively;
(b) a voltage-to-current converting portion between said second power supply and said third power supply and receiving a potential of said first signal for producing a conversion current varying in response to a variation in said potential of said first signal;
(c) a current-to-voltage converting portion connected to said first power supply for converting said conversion current into a first intermediate potential varying within a predetermined range;
(d) a first voltage follower circuit receiving said first intermediate potential for outputting a second intermediate potential;
(e) a current switch receiving said second intermediate potential for outputting a third intermediate potential;
and
(f) a second voltage follower circuit receiving said third intermediate potential for outputting said second signal.

4 more elements

A level converter circuit for converting a first signal at a pseudo-ECL level into a second signal at an ECL level, said level converter circuit comprising:

(a) first, second, and third power supplies for providing a first potential, a second potential lower than said first potential, and a third potential lower than said second potential, respectively;
(b) a current switch between said first power supply and said second power supply and receiving said first signal for producing a first intermediate potential;
(c) a signal generator circuit including
(c-1) a regulating transistor having an emitter, a base receiving said first intermediate potential, and a collector connected to said first power supply, and
(c-2) a regulating resistor having a first end, and a second end connected to said emitter of said regulating transistor,
said signal generator circuit outputting a second intermediate potential at said first end of said regulating resistor;
(d) an output portion receiving said second intermediate potential for outputting said second signal;
(e) a first potential variation detector circuit between said second power supply and said third power supply for applying a first current to said regulating resistor, said first current varying in response to a variation in said third potential relative to said second potential;
and
(f) a second potential variation detector circuit between said first power supply and said third power supply for applying a second current to said regulating resistor, said second current varying in response to a variation in said first potential relative to said third potential.

7 more elements

A level converter circuit for converting a first signal at a pseudo-ECL level into a second signal at an ECL level, said level converter circuit comprising:

(a) first, second, and third power supplies for providing a first potential, a second potential lower than said first potential, and a third potential lower than said second potential, respectively;
(b) a current switch between said first power supply and said second power supply and receiving said first signal for producing a first intermediate potential;
(c) a signal generator circuit including
(c-1) a regulating transistor having an emitter, a base receiving said first intermediate potential, and a collector connected to said first power supply,
(c-2) a first regulating resistor having a first end, and a second end connected to said emitter of said regulating transistor, and
(c-3) a second regulating resistor having a first end, and a second end connected to said first end of said first regulating resistor,
said signal generator circuit outputting a second intermediate potential at said first end of said second regulating resistor;
(d) an output portion receiving said second intermediate potential for outputting said second signal;
(e) a first potential variation detector circuit between said first power supply and said second power supply for applying a first current to said first regulating resistor, said first current varying in response to a variation in said first potential relative to said second potential;
and
(f) a second potential variation detector circuit between said second power supply and said third power supply for applying a second current to said second regulating resistor, said second current varying in response to a variation in said third potential relative to said second potential.

8 more elements

A level converter circuit for converting a first signal at a pseudo-ECL level into a second signal at an ECL level, said level converter circuit comprising:

(a) first, second, and third power supplies for providing a first potential, a second potential lower than said first potential, and a third potential lower than said second potential, respectively;
(b) a current switch between said first power supply and said second power supply and receiving said first signal for producing a first intermediate potential;
(c) a signal generator circuit including
(c-1) a regulating transistor having an emitter, a base receiving said first intermediate potential, and a collector connected to said first power supply, and
(c-2) a first regulating resistor having a first end, and a second end connected to said emitter of said regulating transistor,
said signal generator circuit outputting a second intermediate potential at said first end of said first regulating resistor;
(d) an output portion receiving said second intermediate potential for outputting said second signal;
(e) a second regulating resistor connected between said first power supply and said current switch;
(f) a first potential variation detector circuit between said first power supply and said second power supply for applying a first current to said second regulating resistor, said first current varying in response to a variation in said first potential relative to said second potential;
and
(g) a second potential variation detector circuit between said second power supply and said third power supply for applying a second current to said first regulating resistor, said second current varying in response to a variation in said third potential relative to said second potential.

8 more elements

Dependencies are inferred from the claim text.

Signal processing device and level converter circuit

Life of this patent

Signal processing device and level converter circuit

Life of this patent

Abstract

Claims16