Logic gate with matched output rise and fall times and method of construction

A CMOS differential exclusive-OR gate with highly matched output rise and fall times, comprising:

• a first stacked group of four transistors which comprises:
• a first upper-tier transistor comprising a first upper input, a first upper current node and a second upper current node, the first input to receive an inverse of a first input signal;
• and
• a second upper-tier transistor comprising a second upper input and a third upper current node, the second upper input to receive a second signal, and the second upper current node coupling the first upper-tier transistor to the second upper tier transistor;
• a first lower-tier transistor comprising a first lower input, a first lower current node and a second lower current node, the first lower input to receive an inverse of the second input signal, the first lower current node coupled to the third upper current node;
• and
• a second lower-tier transistor comprising a second lower input and a third lower current node, the second lower input to receive the inverse of the first input signal;
• a complementary stacked group of four transistors which comprises;
• a first complementary upper-tier transistor comprising a first complementary input, a first complementary current node and a second complementary current node, the first complementary input to receive the second input signal, and the first complementary current node coupled to the first current node;
• and
• a complementary second upper-tier transistor comprising a second complementary input, and a third complementary current node coupled to the second complementary current node, and the second complementary input to receive an inverse of the first input signal;
• a first complementary lower-tier transistor comprising a first complementary lower input, a first complementary lower-tier current node coupled to the third current node, and an second complementary lower-tier current node, the first complementary lower-tier input to receive the inverse of the first input signal;
• and
• a second complementary lower-tier transistor comprising a second complementary lower-tier input and a third complementary lower-tier current node coupled to the third lower-tier current node, the second complementary lower-tier input to receive the inverse of the second signal.