Monolithically integrated semiconductor arrangement with a cover electrode

A monolithically integrated semiconductor device having a generally planar weakly-doped semiconductor substrate (2) with first and second main surfaces (3), (4);

• a first zone of a conductivity type opposite to that of said substrate (2) and forming a pn junction with said substrate, said junction extending to said first main surface (3) at an edge portion of said first zone;
• a second zone, whose conductivity type is the same as that of said substrate (2), formed along said first main surface (3) by strong diffusion doping of said substrate, but non-contiguous with said first zone;
• a third zone, whose conductivity type is the same as that of said substrate (2), formed along said second main surface (4) by strong diffusion doping of said substrate, but non-contiguous with each of said first and second zones;
• an insulating passivating layer (5) covering most of said first main surface (3) except for an uncovered area adjacent a surface of said first zone, thereby defining a contact window for said first zone;
• and
• a metallic cover electrode (D) applied to said passivating layer (5) on a side thereof remote from said substrate (2), extending over edge portions of said first and second zones and over that portion of said substrate (2) which is contiguous with said passivating layer (5) between said first and second zones;
• further comprising, in order to increase breakdown voltage of said device between the first zone and the third zone,
• a fourth zone, whose conductivity type is the same as said second zone but less strongly doped, formed to be contiguous with said second zone and with said passivating layer (5) by diffusion doping of said substrate, extending between and separating said second zone from said substrate, with said fourth zone having a uniform surface concentration.