US 5,479,037 AGranted

Low threshold voltage epitaxial DMOS technology

AssigneeSiliconix Incorporated

InventorsFwu-Iuan Hshieh, Hamza Yilmaz, Mike Chang

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Abstract

A low threshold voltage power DMOS transistor structure is disclosed having a lightly doped channel region formed in a shallow layer of relatively lightly doped epitaxial silicon. The light doping of the shallow epitaxial layer minimizes variations in threshold voltage and local variations in punch-through susceptibility due to nonuniformities in epitaxial doping concentration. A relatively heavily doped epitaxial layer is disposed underneath the shallow lightly doped epitaxial layer to reduce the drain to source resistance, R.sub.DS. Because the relatively heavily doped epitaxial layer is located below the channel region and not in the regions of the structure most susceptible to body region punch-through, providing the relatively highly doped epitaxial layer does not cause variations in threshold voltage and does not cause variations in the reverse bias voltage at which punch-through across the body region occurs.

Claims7

Dependent claims

A vertical power MOS transistor structure, comprising:

a substrate layer;
a relatively heavily doped epitaxial layer disposed directly on said substrate layer, said relatively heavily doped epitaxial layer being of a first conductivity type and having a redistribution layer and another layer disposed over said redistribution layer, said another layer having a substantially constant first doping concentration of said first conductivity type, said relatively heavily doped epitaxial layer having been grown with said first doping concentration;
a relatively lightly doped epitaxial layer disposed directly on said relatively heavily doped epitaxial layer, said relatively lightly doped epitaxial layer being of said first conductivity type, said relatively lightly doped epitaxial layer having an upper surface, said relatively lightly doped epitaxial layer having a second doping concentration of said first conductivity type, said second doping concentration being smaller than said first doping concentration, said relatively lightly doped epitaxial layer having been grown with said second doping concentration;
a body region extending through said relatively lightly doped epitaxial layer from said upper surface and into said relatively heavily doped epitaxial layer, said body region being of a second conductivity type opposite said first conductivity type;
a source region disposed in said body region to define a channel region in said relatively lightly doped epitaxial layer at said upper surface, said source region being of said first conductivity type;
a gate insulating layer disposed directly on said upper surface;
and
a gate, disposed at least partly over said channel region and being insulated from said channel region by said gate insulating layer.

5 more elements

A doubly diffused vertical power MOS transistor structure, comprising:

a substrate layer;
a first epitaxial silicon layer disposed directly on said substrate layer and having a redistribution layer and another layer disposed over said redistribution layer, said another layer having a substantially constant first doping concentration of N type dopants, said first epitaxial silicon layer being grown having said first doping concentration of N type dopants;
a second epitaxial silicon layer disposed directly on said first epitaxial layer, said second epitaxial silicon layer being grown having a second doping concentration of N type dopants, said second epitaxial layer having an upper surface, said first doping concentration being greater than said second doping concentration;
a P type body region extending from said upper surface through said second epitaxial silicon layer and into said first epitaxial silicon layer to define an epitaxial silicon region of said first epitaxial silicon layer, said P type body region defining a first lateral outer perimeter of said P type body region and defining a second lateral outer perimeter of said P type body region, said first and second lateral outer perimeters being disposed in respective lateral planes parallel to each other, said lateral plane containing said first lateral outer perimeter being disposed farther from said upper surface than said second lateral outer perimeter, said first and second planes being substantially parallel to said upper surface, said second lateral outer perimeter having a greater outer circumference than said first lateral outer perimeter, said first and second lateral outer perimeters both being disposed in said second epitaxial layer;
an N type source region disposed in said body region and being disposed entirely within said second epitaxial silicon layer, said N type source region defining a minimum distance between said N type source region and said epitaxial silicon region of said first epitaxial silicon layer, said minimum distance extending in a direction somewhat laterally away from said N type source region;
a gate insulating layer disposed directly on said upper surface;
and
a gate disposed at least partly over said gate insulating layer.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/131,114Filed 1 Oct 1993 · continuation
Priority: 4 Aug 1992
Granted: 26 Dec 1995
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 30/635
Vertical IGFETs: having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs
H10D 30/0291
Of double-diffused metal oxide semiconductor [DMOS] FETs: of vertical dmos [vdmos] fets
H10D 30/66
Double-diffused metal-oxide semiconductor [DMOS] FETs: vertical dmos [vdmos] fets
H10D 62/157
Drain regions of DMOS transistors: impurity concentrations or distributions