High performance field effect transistor and method of manufacture thereof
AssigneeUnited Microelectronics Corp.
InventorGary Hong
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Abstract
A method is provided for fabricating a MOSFET transistor device with a gate formed over a lightly doped semiconductor substrate with a gate, and a source region and a drain region. V.sub.T1 ions are uniformly implanted into the surface of the substrate forming a V.sub.T region with substantially uniform doping in the upper portion of the substrate near the surface thereof. A gate oxide layer is formed on the substrate. A gate conductor is deposited over the gate oxide layer. A large angle implant is implanted into the region of the device over the source region. Then ions are implanted to form the source and drain regions which are self-aligned with the gate.
Claims17
A method of fabricating a MOSFET transistor device with a gate formed over a lightly doped semiconductor substrate with a gate, and a source region and a drain region, said method comprising,
- providing a uniform V.sub.T1 ion implant into the surface of said substrate forming a V.sub.T region with substantially uniform doping in the upper portion of said substrate near the surface thereof,
- forming a gate oxide layer on said substrate,
- forming a gate conductor over said gate oxide layer,
- performing a large angle implant into the region of said device over said source region, and
- ion implanting ions to form said source and drain regions which are self-aligned with said gate conductor.
A method of fabricating a MOSFET transistor device with a gate formed over a lightly doped semiconductor substrate with a gate, and a source region and a drain region, said method comprising,
- providing a uniform V.sub.T1 ion implant into the surface of said substrate forming a substantially uniform V.sub.T region in the upper portion of said substrate near the surface said uniform V.sub.T implant region has an implantation of boron or BF2 dopant is performed with a dose between about uniform dose between about 2E11 cm.sup.-2 and about 1E12 cm.sup.-2 with energies between about 20 keV and about 80 keV,
- forming a gate oxide layer on said substrate having a thickness between about 200 .ANG. and about 300 .ANG.,
- forming a gate conductor over said gate oxide layer comprising doped polysilicon having a thickness between about 2,000 .ANG. and about 5,000 .ANG.,
- performing a large angle implant into the region of said device over said source region at an angle .THETA. of between about 20.degree. and about 60.degree. from vertical relative to the surface of said gate oxide layer, said LAI implant employing implanting of boron or BF.sub.2 ions with an energy between about 50 keV and about 150 keV with a dose between about 2E11 cm.sup.-2 and about 2E12 cm.sup.-2, and said source and drain regions ion implanted in a self-aligned pattern by said gate conductor with arsenic (As) ions implanted at an energy between about 30 keV and about 100 keV at a dose between about 1E15 cm.sup.-2 and about 5E15 cm.sup.-2.
Dependencies are inferred from the claim text.