Method for producing patterning alignment marks in oxide
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorYing-Chen Chao
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Abstract
A process for fabricating MOSFET devices, in which a denuded zone in silicon has been created during the normal process sequence, has been developed. In order to avoid the formation of deleterious oxygen precipitates, prior to the creation of the denuded zone, low temperature processing had to be used. Low temperature insulator depositions were used for the alignment mark formation, as well as for the fill for the field oxide regions. Subsequently, high temperature well formation activation anneals, resulted in the creation of the denuded zone, and thus removed the low temperature restriction for the remaining processing steps.
Claims22
A method for fabricating a MOSFET device on a silicon, semiconductor substrate, in which a denuded zone in silicon, is created during the normal processing sequence that consists of:
- depositing a first insulator film on said silicon substrate;
- forming a pattern in said insulator film, and in said silicon, to be used for photolithographic alignment procedures;
- creating a region in said silicon to be used for device isolation;
- depositing second insulator film in said region used for device isolation;
- photoresist patterning to expose a first specific region of said silicon;
- ion implanting a first conductivity imparting dopant into said first exposed region of said silicon;
- photoresist patterning to expose a second specific region of said silicon:
- ion implanting a second conductivity imparting dopant into said second exposed region of said silicon;
- annealing to activate said first conductivity imparting dopant, second conductivity imparting dopant, while creating a denuded zone in said silicon substrate;
- growing a gate oxide on said first exposed silicon region, and on said second exposed silicon region;
- depositing a polysilicon layer on said gate oxide, and on said oxide region used for isolation;
- patterning to form polysilicon gate structures on said gate oxide, in said first exposed silicon region, and in said second exposed silicon region;
- photoresist patterning to expose said first specific region of said silicon;
- ion implanting a third conductivity imparting dopant into said first exposed region of said silicon, and into said polysilicon gate structures;
- photoresist patterning to expose said second specific region of said silicon;
- and
- ion implanting a fourth conductivity imparting dopant into said second exposed region of said silicon, and into said polysilicon gate structures.
A method for fabricating a MOSFET device, on a silicon semiconductor substrate, in which low temperature processing is employed, until the creation of a denuded zone in silicon has been created, comprising the steps of:
- depositing a low temperature, first insulator film on said silicon substrate;
- creating an oxide region in said silicon to be used for device isolation;
- depositing a low temperature, second insulator film in said region used for device isolation;
- photoresist patterning to expose a first region in said silicon, to be used for P well creation;
- ion implanting a first conductivity imparting dopant into said first exposed region in said silicon, to be used for P well creation;
- photoresist patterning to expose a second region in said silicon, to be used for N well creation.
- ion implanting a second conductivity imparting dopant into said second exposed region in said silicon, to be used for N well creation;
- annealing to activate said first conductivity imparting dopant, creating a P well region, second conductivity imparting dopant, creating an N well region, while driving out oxygen from the surface of said silicon substrate to create a denuded zone in said silicon substrate;
- growing a gate oxide on exposed regions of said P well and said N well;
- depositing a polysilicon layer on said gate oxide, and on said oxide region used for device isolation;
- patterning to form polysilicon gate structures on said gate oxide, in said P well and said N well regions;
- photoresist patterning to expose said P well region;
- ion implanting a third conductivity imparting dopant into said P well region, to create N type source and drain regions, and into exposed said polysilicon gate structures;
- photoresist pattening to expose said N well region;
- and
- ion implanting a fourth conductivity imparting dopant into said N well region, to create P type source and drain regions, and into exposed said polysilicon gate structures.
Dependencies are inferred from the claim text.