Process for fabricating a vertical bipolar junction transistor

A process for fabricating a bipolar junction transistor comprising the following steps:

• providing a silicon substrate of a first conductivity type;
• forming, by deposition and etching, a shielding layer having an opening over said silicon substrate;
• implanting ions of a second conductivity type opposite to said first conductivity type into said silicon substrate through said opening to form a lightly-doped base region extending to the underside of said shielding layer by diffusion;
• etching said silicon substrate to form a trench by using said shielding layer as a mask;
• implanting ions of said second conductivity type into said silicon substrate through said trench to form a heavily-doped base region located under the bottom of said trench and extending to contact said lightly-doped base region by diffusion;
• forming, by oxidation, a first oxide thin-layer at the sidewalls of said trench, and a second oxide thin-layer at the bottom of said trench;
• forming a sidewall spacer at the lower corner of said trench;
• forming, by oxidation, an isolation oxide thick-layer at the surfaces uncovered by said shielding layer and said sidewall spacer;
• removing said sidewall spacer, said shielding layer, and said first oxide thin-layer previously covered by said sidewall spacer in order to form a contact window in said trench;
• forming, in said trench, a conductive layer heavily doped by a dopant of said first conductivity type, said dopant diffusing into said lightly-doped base region through said contact window to form an emitter region;
• and
• forming a collector region of said first conductivity type in the upper surface of said lightly-doped base region.