Compressed memory address parity checking apparatus and method

For use in a digital apparatus having a data memory, means for storing data in the data memory at a data memory address having M bits, and means for reading data from an address having M bits in the data memory, a method of checking parity comprising the steps of:

• generating a parity bit for each predetermined set of data bits stored in the data memory;
• storing in an auxiliary memory at an address defined by a predetermined number N of the least significant bits of the M bit address in the data memory at which data is stored the M-N most significant bits of the address in the data memory at which data is stored together with the parity bits generated when said data is stored in the data memory;
• comparing the M-N address bits stored in the auxiliary memory at the address defined by the N least significant bits of the address in the data memory from which data is read with the M-N most significant bits of the address in the data memory from which data is read;
• providing the parity bits stored in the auxiliary memory at the address defined by the N least significant bits of the address in the data memory from which the data is read if there is a match;
• generating a parity bit for each predetermined set of data bits read from the data memory;
• and
• providing the parity bits generated for each predetermined set of data bits read from the data memory if there is no match.

A method of checking the parity of data stored in and read from an address having M bits in a data memory comprising the steps of:

• storing in an auxiliary memory a predetermined number M-N of the most significant bits of the data memory address at which data is stored in the data memory together with one or more parity bits which are generated when the data is stored in the data memory at said data memory address at an address in the auxiliary memory defined by the N least significant bits of said data memory address;
• reading the contents stored at the address in the auxiliary memory defined by the N least significant bits of a data memory address from which data is being read from said data memory, said contents comprising the M-N most significant bits of a data memory address and one or more parity bits;
• comparing the M-N most significant bits of the data memory address read from the auxiliary memory with the M-N most significant bits of the data memory address of data being read from the data memory;
• providing the one or more parity bits stored with the M-N most significant bits of the data memory address being read from the auxiliary memory if there is a match;
• and
• providing one or more parity bits which are generated when the data is read from the data memory if there is no match.

For use in a digital apparatus having a data memory, means for storing data in the data memory at a data memory address having M bits, and means for reading data from an address having M bits in the data memory, a parity checking apparatus comprising:

• means for generating a parity bit for each predetermined set of data bits stored in the data memory;
• means for storing in an auxiliary memory at an address defined by a predetermined number N of the least significant bits of the M bit address in the data memory at which data is stored the M-N most significant bits of the address in the data memory at which data is stored together with the parity bits generated when said data is stored in the data memory;
• first means for comparing the M-N address bits stored in the auxiliary memory at the address defined by the N least significant bits of the address in the data memory from which data is read with the M-N most significant bits of the address in the data memory from which data is read;
• means for disabling the output of the parity checking apparatus an internal parity interrupt signal if the output of said first comparing means indicates that there is no match;
• means for generating a parity bit for each predetermined set of data bits read from the data memory;
• second means for comparing the parity bits stored in the auxiliary memory at the address defined by the N least significant bits of the address in the data memory from which data is read with the parity bits generated when the data is read from the data memory;
• and
• means for generating an internal parity interrupt signal if the output of said second comparing means indicates that there is no match.