Apparatus and method for optimal error correcting code to parity conversion
AssigneeDell USA, L.P.
InventorsTerry J. Parks, Darius D. Gaskins
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Abstract
This invention relates to the general area of data integrety in digital computers. In particular it relates to digital computer systems having parity checked systems busses and ECC checked memory. This invention increases the performance of such systems by reducing the memory latency incurred in the ECC to parity conversion process.
Claims9
A method for converting a plurality of bytes of ECC checked data to a plurality of bytes of parity checked data;
- said ECC checked data having a data portion and a syndrome portion;
- the method comprising the steps:
- (a) checking said plurality of bytes of ECC checked data to determine if any one of said plurality of bytes of ECC checked data has an error;
- (b) generating a parity bit for each of said plurality of bytes of parity checked data from said data portion of said ECC checked data;
- (c) correcting said any one of said plurality of bytes of ECC checked data if said any one of said plurality of bytes contain an error;
- (d) correcting said parity bit data for said any one of said plurality of bytes when an error has been corrected.
A computer system having a system bus electrically connected to a memory system, a processor complex electrically connected to said system bus, and having data error detection and correction for data provided between said memory system and said system bus, said computer system comprising:
- (a) a data portion and a parity portion within said system bus, said parity portion representing the parity of said data portion on said system bus;
- (b) a plurality of digital words within said memory system, said digital words comprising a data portion and an ECC syndrome portion, wherein said syndrome portion represents the syndrome of said data portion of said digital words;
- (c) data correction means for correcting errors in said digital words and providing corrected data, said corrected data being coupled onto said data portion of said system bus;
- (d) parity generation means for generating parity for said corrected data, said parity being coupled to said parity portion of said system bus;
- (e) wherein said data correction means and said parity generation means operate in parallel.
Dependencies are inferred from the claim text.