US 5,477,548 AGranted

Method for testing an integrated circuit means having a hierarchical organization of at least three levels, and integrated circuit means and integrated circuit suitable for being so tested

AssigneeU.S. Philips Corporation

InventorsFranciscus P. M. Beenker, Robertus W. C. Dekker, Rudi J. J. Stans, Max van der Star

Life of this patent

Estimating the term…

Loading patent…

Abstract

A method for testing a hierarchically organized integrated circuit means first attacks each assembly in sequence thereof, and in each assembly executing an assembly test cycle. Each assembly test cycle within the assembly in question attacks each macro thereof in sequence and conditionally executes therein a test run under selective control of a macro test mode (MTM) signal. The number of hierarchy levels may be other than three. The method may be applicable to separate integrated circuits or to a wired board with a plurality of circuits.

Claims12

Dependent claims

A method for testing a digital integrated circuit means that has a hierarchical organization of at least three levels, to wit, at least one assembly on a high level, at least one such assembly being a single digital integrated circuit which comprises on a next lower level a first sequence of subassemblies, at least one of the subassemblies of said first sequence comprising on a lowest level a second sequence of macros, each testable by at least one of a plurality of test types, each macro being selected from a fully combinatorial and completely synchronous operation unit, a fully scannable operation unit in which each flip-flop of said unit is accessible by a scan-chain, and an operation unit which is fully pipelined over its full word width, said method comprising the steps of:

a. collectively resetting said macros to an initial state, by an overall reset signal;
b. in response to an overall macro test mode control signal, entering an assembly test cycle of said at least one such assembly and traversing a first sequence of assignments by successively pointing at subassemblies of said first sequence of subassemblies of said assembly, by a different subassembly enable signal associated with each subassembly, for causing a subassembly test cycle of the subassembly so pointed at to be run until receiving a subassembly ready signal associated with the subassembly;
and
c. after completely traversing said first sequence of assignments, producing an assembly good/faulty indication;
wherein said subassembly test cycle comprises traversing a second sequence of assignments by successively pointing at each macro in said second sequence of macros of said subassembly for causing each macro test type of said plurality applicable to the macro pointed at to be run under control of the overall macro test mode control signal.

2 more elements

A testable digital integrated circuit means that has a hierarchical organization of at least three levels, to wit, at least one assembly on a high level, at least one such assembly comprising on a next lower level a first sequence of subassemblies, at least one of the subassemblies of said first sequence being a single digital integrated circuit and comprising on a lowest level a second sequence of macros, each testable by at least one of a plurality of test types, said device comprising:

a. an input for an overall reset signal for collectively resetting said macros to an initial state;
b. assembly test control means for in response to an overall macro test mode control signal, entering an assembly test cycle of said at least one such assembly and traversing a first sequence of successive assignments of a corresponding sequence of subassembly test control means respectively associated with said first sequence of subassemblies by circulating a first pointer successively pointing at the subassemblies of said first sequence, each assignment being effected by a different subassembly enable signal directed to the subassembly test control means assigned, for running a subassembly test cycle of the associated subassembly until receiving a subassembly ready signal from the associated subassembly;
and
c. first report means for, after completely traversing said first sequence of assignments, producing an assembly good/faulty indication;
wherein said subassembly test control means comprises means for traversing a second sequence of assignments by circulating a pointer successively pointing at each macro in said second sequence of macros of said subassembly for running, under control of the overall macro test mode control signal, each macro test type of said plurality applicable to the macro pointed at, and
wherein, each macro is selected from a fully combinatorial and completely synchronous operation unit, a fully scannable operation unit in which each flip-flop of said unit is accessible by a scan-chain, and an operation unit which is fully pipelined over its full word width.

3 more elements

Dependencies are inferred from the claim text.