Efficient local-bus ROM memory for microprocessor systems
AssigneeLSI Logic Corporation
InventorThomas J. Wilson
Life of this patent
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Abstract
An efficient technique for providing ROM memory on a microprocessor local bus is described whereby a ROM and all necessary address decoding and control circuitry is incorporated in a single integrated circuit. By doing this, only one chip is required to add ROM to a microprocessor local bus, saving considerable space and power over discrete implementations. The ROM is implemented in a wide memory format, matching the bus width of the microprocessor to which it is connected. This permits full-speed access to the local bus ROM, and eliminates any need for such techniques as ROM "shadowing".
Claims10
A single chip local-bus read only memory device comprising:
- an integrated circuit;
- a read only memory on the integrated circuit having data outputs, first address inputs, and an enable signal input, said read only memory being operative to produce a data value on its data outputs corresponding to a first portion of an external address signal at its first address inputs when the enable signal is asserted;
- a programmable address on the integrated circuit;
- means for programming the programmable address;
- address decode and select logic on the integrated circuit, operable to compare a second portion of the external address signal to the programmable address, to monitor a set of external control signals and to assert the enable signal when the second portion of the external address signal matches the programmable address and a pre-determined combination of external control signals occurs.
A single chip local-bus read only memory device comprising:
- an integrated circuit;
- a read only memory on the integrated circuit having data outputs, first address inputs, and an enable signal input, said read only memory being operative to produce a data value on its data outputs corresponding to a first portion of an external address signal at its first address inputs when the enable signal is asserted;
- external signals providing a comparison address;
- address decode and select logic on the integrated circuit, operable to compare a second portion of the external address signal to the comparison address, to monitor a set of external control signals, and to assert the enable signal when the second portion of the external address signal matches the comparison address and a pre-determined combination of external control signals occurs.
A method of providing read only memory on a microprocessor local-bus, comprising the steps of:
- providing an integrated circuit;
- providing a read only memory on the integrated circuit having data outputs, first address inputs, and an enable signal input, said read only memory being operative to produce a data value on its data outputs corresponding to a first portion of an external address signal at its first address inputs when the enable signal is asserted;
- providing a programmable address on the integrated circuit;
- providing means for programming the programmable address;
- providing address decode and select logic on the integrated circuit;
- comparing, in the address decode and select logic, a second portion of the external address signal to the programmable address;
- monitoring, in the address decode and select logic, a set of external control signals;
- and
- asserting the enable signal when the second portion of the external address signal matches the programmable address and a pre-determined combination of external control signals occurs.
A method of providing read only memory on a microprocessor local bus, comprising the steps of:
- providing an integrated circuit;
- providing a read only memory on the integrated circuit having data outputs, first address inputs, and an enable signal input, said read only memory being operative to produce a data value on its data outputs corresponding to a first portion of an external address signal at its first address inputs when the enable signal is asserted;
- providing a programmable address on the integrated circuit;
- providing an externally generated comparison address;
- providing address decode and select logic on the integrated circuit;
- comparing, in the address decode and select logic, a second portion of the external address signal to the comparison address;
- monitoring a set of external control signals;
- and
- asserting the enable signal when the second portion of the external address signal matches the programmable address and a pre-determined combination of external control signals occurs.
Dependencies are inferred from the claim text.