Semiconductor RAM device with a single write signal line for one column in memory cell array and for one port

A random access memory device having a plurality of ports and a memory cell array which comprises:

• a plurality of memory cells arranged in rows and columns of a matrix, each memory cell comprising
• a data holding element having first and second terminals disposed at opposite sides of the data holding element in a row direction, a high level and a low level signal being simultaneously applied to said first and second terminals respectively,
• an inverter circuit directly connected between the first and the second terminals,
• a first writing gate provided for a first one of said ports and being connected to said first terminal, and
• a second writing gate provided for a second one of said ports and being connected to said first terminal;
• a first writing word line for said first one of the ports extending along each of said rows and being connected to said first writing gate of each of said memory cells in each of said rows for controlling said first writing gate, said first writing gate being opened when said first writing word line is activated;
• a first write signal line extending as a single line for said first port, said first write signal line being connected to said first writing gate of each of the memory cells in each of said columns, whereby a first data signal from said first write single line is applied to said first terminal of said data holding element in each of said memory cells when said first writing gate is opened, said first data signal being inverted by said inverter circuit and being applied to said second terminal of said data holding element;
• and
• a second write signal line extending as a second single line for said second port, said second write signal line of said second single line being connected to said second gate of each of said memory cells in each of said columns, whereby a second data signal transmitting from said second port onto said second single line is applied to said first terminal of said holding element in each of said memory cells when said second gate is opened, said second data signal being inverted by said inverter circuit and being applied to said second terminal of said data holding element.

A single port RAM having a plurality of memory cells arranged in m rows and n columns, wherein m and n are positive integers greater than one, each of said memory cells comprising:

• only one bit line;
• a word line;
• a flip-flop having first and second terminals disposed at opposite sides of the flip-flop in a row direction;
• a first transistor connected between said single bit line and said first terminal of said flip-flop, a gate of said first transistor being connected to said word line;
• and
• an inverter directly connected between said first and second terminals such that a data signal applied to said first terminal of said flip-flop through said bit line is inverted by said inverter and applied to said second terminal of said flip-flop.

A memory device having a plurality of memory cells, each cell having at least first and second writing ports and one reading port, comprising:

• first and second writing word lines;
• first and second write signal bit lines;
• each of said memory cells comprising
• a data holding element having first and second terminals disposed at opposite sides of the data holding element in a row direction;
• first and second gates, said first gate connected between said first terminal and the first write signal bit line and said second gate connected between said first terminal and the second write signal bit line wherein said first gate is controlled by said first writing word line and said second gate is controlled by said second writing word line;
• and
• an inverter directly connected between the first and second terminals.