US 5,477,499 A · Memory architecture for a three volt flash EEPROM

Abstract

A flash EEPROM array includes a plurality of flash EEPROM cells and the flash EEPROM array has both a low power supply voltage V.sub.CC and high speed performance. This high speed performance is achieved by utilizing overerasure, a condition that was previously viewed as making a flash EEPROM cell inoperative, Specifically, the integrated circuit of this invention includes a flash EEPROM array wherein each flash EEPROM cell is overerased, and circuit means which erases, reads, and programs the overerased flash EEPROM cells. In each operation, the circuit means isolates all of the flash EEPROM cells in the array except a selected flash EEPROM cell so that leakage currents do not affect the flash EEPROM cell selected for the operation. The ability to perform the read operation on an overerased flash EEPROM cell is the mechanism that maintains the speed performance of the flash EEPROM array with the low power supply voltage.

Claims41

Dependent claims

A non-volatile memory structure comprising:

a plurality of flash electrically erasable read-only memory (EEPROM) cells;
a plurality of bit lines;
and
a plurality of word lines wherein each flash EEPROM cell is connected to one of said plurality of word lines and to one of said plurality of bit lines;
an overerasure circuit operatively connected to said plurality of word lines and to said plurality of bit lines wherein upon erasure of a flash EEPROM cell, said overerasure circuit applies voltages to the word line and to the bit line connected to said flash EEPROM cell such that said flash EEPROM cell has a negative delta threshold thereby placing said flash EEPROM cell in an overerased condition.

2 more elements

Dependencies are inferred from the claim text.

Memory architecture for a three volt flash EEPROM

Life of this patent

Memory architecture for a three volt flash EEPROM

Life of this patent

Abstract

Claims41