Semiconductor memory device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTsukasa Ooishi
Life of this patent
Estimating the term…
Abstract
A sense amplifier including a pair of NMOS transistors connected in series between a pair of bit lines differential-amplifies the potential difference between the pair of bit lines by reducing the source potentials of the NMOS transistors to ground potential. An NMOS transistor is activated for a predetermined time after initiation of a differential amplification by the sense amplifier, whereby the source potentials of the NMOS transistors are controlled so as to attain a potential lower than the ground potential during that predetermined time. As a result, the operation margin of the NMOS transistors is increased during the predetermined time period.
Claims7
A semiconductor memory device formed on a semiconductor substrate, comprising:
- a memory cell storing charge representing data,
- a pair of bit tines connected to said memory cell and from which a potential difference is generated therebetween according to said charge,
- first differential amplify means including a pair of MOS transistors connected in series between said pair of bit lines for differential-amplifying the potential difference between said pair of bit lines by reducing the potentials of the sources of said pair of MOS transistors and reducing the potential of one of said pair of bit lines having a lower potential to a first potential,
- second differential amplify means including a pair of MOS transistors connected in series between said pair of bit lines for differential-amplifying the potential difference between said pair of bit lines by increasing the potentials of the sources of said pair of MOS transistors, and increasing the potential of one of said pair of bit lines having a higher potential to a second potential,
- first potential control means for controlling the substrate potentials of said pair of MOS transistors of said first differential amplify means so as to attain a third potential lower than said first potential, after the potential of one of said pair of bit lines having a lower potential is brought to said first potential by said first differential amplify means, and
- second potential control means for controlling the substrate potentials or said pair of MOS transistors of said second differential amplify mean so as to attain a fourth potential higher than said second potential, after the potential of one of said pair of bit lines having a higher potential is brought to said second potential by said second differential amplify means.
A method of operating a semiconductor memory device including a pair of bit lines connected to a memory cell and having a potential difference generated therebetween according to charge transmitted from said memory cell, first differential amplify means having a pair of MOS transistors connected in series between said pair of bit lines for differential-amplifying the potential difference between said pair of bit lines by reducing the source potentials of said pair of MOS transistors, and for reducing the potential of one of said pair of bit lines having a lower potential to a first potential, and second differential amplify means having a pair of MOS transistors connected in series between said pair of bit lines for differential-amplifying the potential difference between said pair of bit lines by increasing the source potentials of said pair of MOS transistors, and for increasing one of said pair of bit lines having a higher potential to a second potential, said method comprising the steps of:
- controlling the substrate potentials of said pair of MOS transistors of said first differential amplify means so as to attain a third potential lower than said first potential, after the potential of one of said pair of bit lines having a lower potential is brought to said first potential by said first differential amplify means, and
- controlling the substrate potentials of said pair of MOS transistors of said second differential amplify means so as to attain a fourth potential higher than said second potential, after the potential of one of said pair of bit lines having a higher potential is brought to said second potential by said second differential amplify means.
Dependencies are inferred from the claim text.