Semiconductor memory device

A semiconductor memory device, comprising:

• a first PNP transistor having an emitter coupled to a signal transport line, a base, and a collector;
• a second PNP transistor having an emitter coupled to an inverted signal transport line, a collector coupled to said base of said first PNP transistor, and a base coupled to said collector of said first PNP transistor;
• a first current limiter connected between said collector of said first PNP transistor and a reference potential;
• a second current limiter connected between said collector of said second PNP transistor and said reference potential;
• a first constant current source connected between a supply voltage and said emitter of said first PNP transistor;
• and,
• a second constant current source connected between said supply voltage and said emitter of said second PNP transistor.

A semiconductor memory device, comprising:

• a first current limiter coupled to a supply voltage;
• a second current limiter coupled to said supply voltage;
• a first NMOS transistor having a drain electrode coupled to said first current limiter, a gate electrode coupled to said second current limiter, and a source electrode coupled to a signal transport line;
• second NMOS transistor having a drain electrode coupled to said gate electrode of said first NMOS transistor and to said second current limiter, a gate electrode coupled to said drain electrode of said first NMOS transistor and to said first current limiter, and a source electrode coupled to an inverted signal transport line;
• a first constant current source connected between said source electrode of said first NMOS transistor and a reference potential;
• and,
• a second constant current source connected between said source electrode of said second NMOS transistor and said reference potential.

A semiconductor memory device, comprising:

• a first current limiter coupled to a supply voltage;
• a second current limiter coupled to said supply voltage;
• a first NPN transistor having a collector coupled to said first current limiter, a base coupled to said second current limiter, and an emitter coupled to a signal transport line;
• a second NPN transistor having collector coupled to base of said first NPN transistor and to said second current limiter, a base coupled to said collector of said first NPN transistor and to said first current limiter, and an emitter coupled to an inverted signal transport line;
• a first constant current source connected between said emitter of said first NPN transistor and a reference potential;
• and,
• a second constant current source connected between emitter of said second NPN transistor and said reference potential.