Nonvolatile semiconductor memory apparatus

A nonvolatile semiconductor memory apparatus, comprising:

• a plurality of memory cells being electrically rewritable, each having a MOS transistor including a drain, a source and a control gate, so connected in series that said drain of one transistor and said source of another transistor adjacent thereto are formed in a shared region to form a memory cell array having a drain end and a source end, said memory cell array being divided into a plurality of blocks;
• a first selective gate transistor having a first end and a second end connected to said drain end;
• a bit line connected to said first end of said first selective gate transistor;
• a second selective gate transistor connected to said source end;
• and
• charging means for charging said control gate of at least one nonselective memory cell included in one of said blocks earlier than at least one of said first and second selective gate transistors.

An electrically erasable nonvolatile memory device comprising:

• a memory cell array including a plurality of memory cells, each comprising a MOS transistor having a control gate, said plurality of said memory cells constituting a memory cell unit which has two end portions;
• a selective gate transistor having a selective gate and being coupled to one end portion of said memory cell unit;
• a bit line coupled to said memory cell unit via said selective gate transistor;
• a source line coupled to the other end portion of said memory cell unit;
• and
• charging means for charging control gates of the MOS transistor prior to charging said selective gate of said selective gate transistor.