Semiconductor memory device with a self-initializing circuit operable after supply of power
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorAkihiro Shirai
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Abstract
An improved DRAM includes an internal circuit to be initialized upon start of supply of a supply voltage. The DRAM includes a dummy clock signal generator, and applies a dummy clock signal to a clock signal generator through a switching circuit until a predetermined time period elapses after the start of supply of the supply voltage by a timer circuit. A signal /RAS is controlled in a special manner, is not required for initializing an internal circuit such as a refresh counter. Therefore, a load required in the external circuit for initialing the DRAM is reduced.
Claims12
A semiconductor memory device comprising:
- an internal circuit to be initialized upon start of supply of a supply voltage;
- initialization control means for initializing and control said internal circuit in response to an applied clock pulse;
- a timer circuit detecting elapse of a redetermined time length after the start of supply of the supply voltage and supplying a switching control signal;
- internal clock pulse generating means for receiving the supply voltage and generating the internal clock pulse;
- and
- a transfer gate circuit receiving an externally applied state control clock pulse and the internal clock pulse, and responsive to said switching control signal from said timer circuit for selectively applying one of said externally applied state control clock pulse and said internal clock pulse to said initialization control means.
A dynamic random access memory device comprising:
- a memory cell array including a plurality of memory cells disposed in rows and columns;
- a refresh counter for generating a refresh count signal for refreshing a data signal stored in said memory cell array;
- a reset circuit for resetting said refresh counter in response to an applied clock pulse;
- a timer circuit supplied with a supply voltage for detecting elapse of a predetermined time length after supply of the supply voltage and supplying a switching control signal;
- a ring oscillator supplied with the supply voltage for generating a dummy clock pulse for operating said memory device under a dummy cycle;
- and
- a transfer gate circuit receiving the dummy clock pulse and an externally applied row address strobe signal, and response to said switching control signal supplied from said timer circuit for selectively supplying one of said dummy clock pulse and said row address strobe signal to said reset circuit,
- said transfer gate applying the dummy clock pulse to said reset circuit during said predetermined time length after the start of supply of the supply voltage and applying the row address strobe signal to said reset circuit after the elapse of said predetermined time length.
Dependencies are inferred from the claim text.