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US 5,477,490 AGranted
Memory control device
AssigneeFujitsu Limited
InventorsHirotomo Miyawaki, Noriyuki Suzuki, Shigeatsu Samukawa, Masahiro Shirai, Naomi Ikeda
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AssigneeFujitsu Limited
InventorsHirotomo Miyawaki, Noriyuki Suzuki, Shigeatsu Samukawa, Masahiro Shirai, Naomi Ikeda
Estimating the term…
An elastic memory determines an amount of delay of input data relative to other input data according to a phase difference between synchronous pulses each indicating a header of a frame of the associated input data. The elastic memory thus synchronizes both input data in the channel level. Both input data are time-division multiplied by a first multiplier. On the other hand, each counter receives synchronous pulses and thereby counting up to make a ROM produce address value of which order is determined previously according to the counted value. These address values are multiplied by a second multiplier. A decoder controls a RAM, a high-impedance control unit and a flip-flop to write in and read out of the RAM the input data. The read data are divided by a signal restoring device.
A memory control device that receives a fixed length data consisting of a plurality of continuous unit data to store said fixed length data in storing means and that reads the unit data out of the storing means in a predetermined order to produce the fixed length data comprising:
A memory control method comprising:
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
Term ended 11 Aug 2014 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
This invention relates to a memory control device. More particularly, this invention relates to a control device used between two systems that each is based on different data format from the other's for converting a format of an input data into any adequate format to produce an output data having the converted format.
2. Description of the Invention
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:
FIG. 1 is a block diagram showing a structure of a first embodiment of the present invention;
FIG. 2 is a block diagram showing a structure of a second embodiment of the present invention;
FIG. 1 shows a memory control device according to a first embodiment of the present invention.
This device is an embodiment where a head timing of unit data forming input data of one sequence is synchronized with a head timing of unit data forming input data of other sequence and where these input data are multiplied and written in a memory.
The memory control device is supplied with a plural sequences of input data, i.e., a first input data (DATA1IN) and a second input data (DATA2IN). The memory control device comprises a receiving unit 102 for receiving these input data first, a delaying device 103 connected to the receiving unit 102, a multiplier 104 connected to the receiving unit 102 and the delaying device 103, a storing device 101 connected to the multiplier 104, a writing address designating device 105 and a reading address designating device 106 each connected to the storing device 101, and a restoring unit 107 connected to the storing unit 101 for producing a first output data (DATA1OUT) corresponding to the first input data (DATA1IN) and a second output data (DATA2OUT) corresponding to the second input data (DATA2IN).