US 5,477,489 A · High-stability CMOS multi-port register file memory cell with column isolation and current-mirror row line driver

Abstract

A memory cell has the read current from the bit lines isolated from the bistable storage latch in the cell. Internal nodes of the bistable storage latch control isolated gates of MOS read transistors which gate the read current from the bit lines to a local node within the memory cell. The read current is then switched to ground from the local node by a read switch transistor. The read switch transistor is gated by the read row line. The read current is isolated from the read row line because the read row line is only connected to the isolated gate of the read switch transistor. The read current is also isolated from the bistable storage latch since the read transistors are connected at their isolated MOS gates to the bistable's nodes. This isolation of the read current allows additional read ports to be added without disrupting the cell's stability or write performance. The read ports are optimized independently of the bistable stability and write performance and even optimized independently of other read ports. For allowing better control of the read currents, a current-mirroring row driver causes the current in the row driver to be mirrored by the read currents flowing through the read switch transistors.

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Claims21

Dependent claims

A multi-port memory comprising:

a read row line for activating a row of memory cells;
and
a memory cell in said row of memory cells comprising:
bistable storage means, having two stable states, for storing a bit of data;
write means for changing from a first of said two stable states to a second of said two stable states of said bistable storage means;
read port means for reading which of said two stable states is stored in said bistable storage means, said read port means comprising:
differential read means for gating a read current in response to said bistable storage means, said differential read means isolating said bistable storage means from said read current wherein said read current is prevented from disturbing said bit of data stored in said bistable storage means;
and
read switch means, receiving said read current from said differential read means, for switching said read current to a current sink in response to said read row line, said read switch means isolating said read current from said read row line,
whereby said read current flows through said differential read means and said read switch means to said current sink, but said read current is isolated from said bistable storage means and said read row line.

7 more elements

A multi-port memory comprising:

a write row line for selecting a row of memory cells for writing;
write bit lines for transmitting a bit of data to a memory cell for writing to said memory cell;
a read row line for activating said row of memory cells for reading to a first read port;
a first pair of read bit lines for transmitting said bit of data in said memory cell for sensing by a sense amplifier for said first read port;
said memory cell in said row of memory cells comprising:
storage means for storing said bit of data, said storage means having a first internal node and a complement internal node;
write pass transistors, coupled to conduct current between said write bit lines and in response to said write row line;
a local node within said memory cell, said local node separate from said first internal node and said complement internal node;
isolated read transistors, having isolated control gates coupled to said first internal node and said complement internal node, for conducting a read current from said first pair of read bit lines to said local node;
a read switch transistor, for switching said read current from said local node to a current sink in response to said read row line, said read switch transistor having an isolated control gate coupled to said read row line;
wherein said read current is supplied from one of said first pair of read bit lines when said read row line is in an active state, said bit of data determining which read bit line of said first pair of read bit lines will supply said read current, said sense amplifier sensing which read bit line of said first pair of read bit lines supplies said read current and outputting said bit of data in response.

8 more elements

Dependencies are inferred from the claim text.

Description6,988 words

Summary2,656 words

#This invention relates to CMOS memory cells, and more particularly to a memory cell with multiple ports and isolation read transistors.

#This application is related to "BiCMOS Static RAM with Active-Low Word Line", filed Aug. 31, 1994, U.S. Ser. No. 08/298,593, having a common inventor and assigned to the same assignee.

#Random access memories (RAMs) have increased in speed and density at a rapid pace. Complementary metal-oxide-semiconductor (CMOS) devices have been used extensively in constructing arrays of memory storage cells. CMOS technology provides very high densities of memory cells using n-channel and p-channel MOS transistors.

Brief description of the drawings6 figures

#FIG. 1 shows a typical prior-art 6-transistor cell.

#FIG. 2 shows read ports isolated from the cell's storage latch.

#FIG. 3 highlights the prior-art problem with read current flowing through row lines.

Detailed description4,254 words

#The present invention relates to an improvement in memory cells. The following description is presumed to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparel to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

#FIG. 4 is a schematic diagram of a multi-port memory cell with current isolation. Cell 400 contains storage latch 302 composed of cross-coupled CMOS inverters. This storage latch 302 has two stable states and is sometimes referred to as a bistable. A first stable state occurs after a relatively high voltage is written to node 348 of storage latch 302, while a second stable state occurs after a relatively low voltage has been written to node 349 of storage latch 302. A low voltage applied to a bit line is often ground or a voltage transitioning toward ground, while a high voltage applied to a bit line can be 3.3 volts, or a transistor threshold below the power supply. Just a slight difference in the low and high voltages seen inside the cell at nodes 348, 349 is enough to change the state of the cell, especially when two bit lines with a voltage difference are applied to the bistable during a write. For clarity, one write port and two read ports are shown for cell 400 of FIG. 4, although the number of read and write ports can be varied.

#Cell 400 can be broken down into several functional groups of transistors:

Facts

Application

08/407,505Filed 20 Mar 1995

Granted

19 Dec 1995

Term ended

20 Mar 2015

Estimated · how

Pre-1995 term; greater of 17 years from grant or 20 years from filing when eligible. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification2 codes

G11C 8/16
Arrangements for selecting an address in a digital store: multiple access memory array, e.g. addressing one storage element via at least two…
G11C
Static stores

High-stability CMOS multi-port register file memory cell with column isolation and current-mirror row line driver

Life of this patent

High-stability CMOS multi-port register file memory cell with column isolation and current-mirror row line driver

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims21

Description6,988 words

Drawings

Classification2 codes

Life of this patent

Description6,988 words