System, a memory and a process having bit processing circuits associated with memory for pre-processing data read by a processor

#This invention relates generally to electronic systems that have a processor on a semiconductor substrate for processing data and memory on a separate semiconductor substrate or substrates for storing data, and particularly relates to reducing the time required for processing data by locating some bit processing circuits on the memory semiconductor substrate to perform some pre-processing of data read from the memory by the processor.

#Central processing units (CPUs) available today are extremely fast and demand high speed memories to keep up with the processing speeds. A significant amount of the processing unit's time is spent in memory access, in terms of waiting time due to generation, transmission and reception of control and data signals transferred across the memory bus and inherent delays in accessing the array of memory cells. Some of the solutions proposed to overcome these limitations include parallel processing, high speed memory parts, and cache memory; these solutions improve the CPU-memory bandwidth but add cost to the system implementation or to the memory.

#Considering a system using some of the fastest dynamic random access memory (DRAM) parts available, a memory read cycle requires about 50 nanoseconds to address, access and read a word of data from the part back to the CPU. The CPU then requires some time to process the word of data and another 50 nanosecond memory cycle to write the word of data back to the memory part. This executes a READ-MODIFY-WRITE cycle.

#FIG. 1 is a simplified block diagram of a computer system including a central processing unit and memory according to one aspect of the invention;

#FIG. 2 is another simplified block diagram of a computer system including a central processing unit and memory according to another aspect of the invention;

#FIG. 3 is an idealized block diagram of a memory part implementing the invention;

#In FIG. 1, computer system 20 comprises central processing unit 22, bit operation memory 24, peripheral circuits 26 and I/O circuits 28. Memory 24 contains circuits for performing bit operations on the contained data and can be formed of an integrated circuit on a single substrate or can be formed of plural integrated circuits on plural substrates, or parts 30, connected together in known manner. In system 20, the row addresses, column addresses and bit operation codes or bit opcode signals occur on a single set of leads 32 in time multiplexed order. The data signals occur on leads 34 and the control signals occur on leads 36. In this embodiment, the CPU passes the bit opcodes or instructions to the memory 24 and the memory receives the bit opcodes across the leads 32 after the time ordered row and column information. This avoids conflict with the normal operation of the memory 24.

#In FIG. 2, computer system 38 comprises central processing unit 22, bit operation memory 40, peripheral circuits 26 and I/O circuits 28. Memory 40 also contains circuits for performing bit operations on the contained data and can be formed of an integrated circuit on a single substrate or can be formed of plural integrated circuits on plural substrates, or parts 42, connected together in known manner. In system 38, the row addresses and column addresses signals occur on a single set of leads 44 in normal time multiplexed order. The data signals occur on leads 34 and the control signals and bit opcodes occur on leads 46. In this embodiment, the CPU passes the bit opcodes or instructions to the memory 40 across the leads 46 on separate control leads connected to the normally not-connected (NC) leads on the memory 40 or parts 42. This avoids the transfer of the bit opcodes from interfering with the normal operation of the memory 40 or parts 42.

#The present invention can be used in a family of DRAM devices constructed and arranged to contain 1,048,576 words of data having sixteen parallel bits in a word, also identified by the abbreviation 1M.times.16.