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AssigneeHitachi, Ltd.
InventorsKoichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
Estimating the term…
A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.
A memory device formed on an IC chip, comprising:
A memory device with operation function, formed on one chip as an integrated device, comprising:
A memory device formed on an IC chip, comprising:
A memory device with operation function, formed on one chip as an integrated device, comprising:
A memory device on an IC chip responsive to an access from an external side of the IC chip, comprising:
A memory device on an IC chip having a data terminal, an address terminal, and a control terminal, comprising:
A memory device on an IC chip having a data terminal, an address terminal, and a control terminal, comprising:
A memory device on an IC chip having a data terminal, an address terminal, and a control terminal, comprising:
A memory device on an IC chip having a data terminal, an address terminal, and a control terminal, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556…
General purpose image data processing: processor architectures; Processor configuration, e.g. pipelining
General purpose image data processing: memory management
Control of the bit-mapped memory: arrangements for updating the contents of the bit-mapped memory
Term ended 19 Dec 2012 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
The present invention relates to a memory device, and in particular, to a memory device suitable for a graphic memory to be utilized in high-speed image processing.
The prior art technique will be described by referring to graphic processing depicted as an example in FIGS. 1-2. For example, the system of FIG. 1 comprises a graphic area M1 having a one-to-one correspondence with a cathode ray tube (CRT) screen, a store area M2 storing graphic data to be combined, and a modify section FC for combining the data in the graphic area M1 with the data in the store area M2. In FIG. 2, a processing flowchart includes a processing step S1 for reading data from the graphic area M1, a processing step S2 for reading data from the store area M2, a processing step S3 for combining the data read from the graphic area M1 and the data read from the store area M2, and a processing step S4 for writing the composite data generated in the step S3 in the graphic area M1.
In the graphic processing example, the processing step S3 of FIG. 2 performs a logical OR operation only to combine the data of the graphic area M1 with that of the store area M2.
FIG. 1 is a schematic block diagram for explaining an operation to generate a composite graphic image in a graphic data processing system.
FIG. 2 is a flowchart of processing applied to the prior art technique to generate composite graphic data.
FIG. 3 is a schematic block diagram for explaining multivalued graphic data processing.
Referring to the accompanying drawings, the following paragraphs describe embodiments of the present invention in detail.
FIG. 4 is a timing chart of a DRAM. First, the operation to access the memory will be briefly described in conjunction with FIG. 4. In this timing chart, ADR is an address signal supplied from an external device and WR indicates a write request signal. These two signals (ADR and WR) are fed from a microprocessor, for example. In addition, RAS is a row address strobe signal, CAS is a column address strobe signal, A indicates an address signal representing a column or row address generated in the timesharing fashion, WE stands for a write enable signal, and Z is a data item supplied from an external device (microprocessor). Excepting the Z signal, they are control signals generated by a DRAM controller, for example. The memory access outlined in FIG. 4 can be summarized as follows.
(i) As shown in FIG. 4, a memory access in a read/write cycle generally commences with a read cycle (I)and ends with a write cycle () due to a write enable signal, WE.