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US 5,477,484 AGranted
Semiconductor memory having a high speed sense amplifier
AssigneeNEC Corporation
InventorYasuhiro Nakashima
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AssigneeNEC Corporation
InventorYasuhiro Nakashima
Estimating the term…
A semiconductor memory comprises a memory cell array including a plurality of digit lines, a plurality of word lines, a plurality of memory cells located at intersections between the digit lines and the word lines, and a column selection circuit for selecting one digit line from the digit lines in accordance with a selection signal. A sense amplifier includes a first P-MOS transistor for precharging a digit line selected by the column selection circuit, an inverting amplifier having an input connected to receive a signal on the selected digit line, and a second P-MOS transistor having a gate and a drain connected to an output and an input of the inverting amplifier, respectively. A gate-grounded third P-MOS transistor maintained in a conductive condition is connected at its source to a voltage supply voltage and at its drain connected to a source of the P-MOS second transistor. The third P-MOS transistor has an on-resistance larger than that of the second transistor and substantially the same current driving capability as that of the second transistor.
A semiconductor memory comprising:
A semiconductor memory comprising:
Dependencies are inferred from the claim text.
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Sense amplifiers; Associated circuits , e.g. timing or triggering circuits: single-ended amplifiers
Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits
Static stores
Term ended 1 Dec 2014 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a semiconductor memory including a sense amplifier for reading out binary information stored in a memory cell in the form of a conductive/non-conductive condition.
2. Description of Related Art
FIG. 1 is a circuit diagram of a conventional semiconductor memory incorporating therein the current detection type sense amplifier;
FIG. 2 is a timing charge illustrating an operation of the semiconductor memory shown in FIG. 1;
FIG. 3 is a circuit diagram similar to that of FIG. 1 but illustrating a first embodiment of the semiconductor memory in accordance with the present invention; and
Referring to FIG. 3, there is shown a circuit digram similar to that of FIG. 1 but illustrating a first embodiment of the semiconductor memory in accordance with the present invention. In FIG. 3, elements similar to those shown in FIG. 1 are given the same Reference Numerals, and explanation thereof will be omitted for simplification of the description.
As seen from comparison between FIGS. 1 and 3, the first embodiment shown in FIG. 3 has the same memory cell array 10 as that of the conventional example shown in FIG. 1 and the same column selection circuit 20 as that of the conventional example shown in FIG. 1. The first embodiment shown in FIG. 3 has a sense amplifier 40 different from the sense amplifier 30 of the conventional example shown in FIG. 1.
As also seen from comparison between FIGS. 1 and 3, the sense amplifier 40 is different from the sense amplifier 30 in that a pair of P-channel field effect transistors Tr32 and Tr33 is provided in place of the transistor Tr32x in the sense amplifier 30 shown in FIG. 1.