Multiplying system having multi-stages for processing a digital signal based on the Booth's algorithm

In a method for processing a digital signal based on the Booth's algorithm within a multiplying system having multiple stages of multipliers wherein the improvement comprises the steps of:

• inputting coefficients Y into a single Booth decoder in sequence corresponding to each of said multiple stages for processing a multiplicand X, with said coefficients Y being consecutively processed to generate an output for each stage;
• memorizing in a storage element the generated output of said Booth decoder corresponding to each of said multiple stages,
• inputting a multiplicand X into each stage and multiplying it by the output of said Booth decoder which has been memorized for each such stage;
• adding the product of the multiplication in each of said multiple stages to the output of the preceding stage to establish a predetermined time delay for the product of the addition and supplying the time delayed product to the next consecutive stage so as to output a delayed product in the last stage as a result of the signal processing.

In a multiplying system having multi-stages of multipliers for processing a digital signal based on the Booth's algorithm, the improvement which comprises:

• a single Booth decoder for processing a coefficient Y input corresponding to each of said multi-stages in which a multiplicand X is inputted to generate a multiplied output as a processed product;
• a plurality of arithmetic processing units connected in series and a series of delay elements for forming a predetermined time delay for each of said multi-stages in consecutive sequence so as to provide a delayed output from said Booth decoder for each stage corresponding to the delayed output in the preceding stage;
• and
• an adder for adding the products of the multiplication, wherein
• each of said arithmetic processing units comprises a storage element for memorizing an output of said Booth decoder corresponding to each of the multi-stages, a delay element for providing a predetermined time delay to an output of the delay element of the preceding arithmetic processing unit, means for supplying the delayed product to the following delay element, and a multiplier which does not incorporate a Booth decoder for multiplying an output of the delay element of the preceding processing unit by the output of said Booth decoder memorized in the storage element of the present arithmetic unit.

In a multiplying system having multi-stages for processing a digital signal, based on the Booth's algorithm, the improvement comprising:

• a single Booth decoder for processing a coefficient Y inputted corresponding to each of said multi-stages using a multiplicand X to generate an output to be multiplied and subsequently outputted as a processed product;
• a plurality of arithmetic processing units connected in series, for multiplying a multiplicand X by an output from said single Booth decoder for each of said multi-stages, adding the product of the multiplication to the delayed output in the preceding stage, giving a predetermined time delay to the product of the addition, and subsequently supplying the delayed product to the next consecutive processing unit,
• wherein each of said arithmetic processing units comprises a storage element for memorizing an output of said Booth decoder corresponding to each of the multi-stages, a multiplier which includes no Booth decoder for multiplying an inputted multiplicand X by the output of said Booth decoder memorized in said storage element, an adder for adding the product of the multiplication of said multiplier to the delayed output of the preceding arithmetic processing unit, a delay element for giving a predetermined time delay to the output of said adder and means for supplying the delayed product to the arithmetic processing unit for the following stage.