Data shifting circuit by utilizing MOS barrel shifter

A data shifting circuit for shifting n-bit data by a MOS transistor array comprising:

• an input bus for inputting the n-bit data to be processed;
• a first bus for inputting the data to be processed, which is inputted from said input bus, to said MOS transistor array;
• a second bus for inputting the data to be processed, which is inputted from said input bus, to said MOS transistor array;
• a bus switching circuit for connecting said input bus to said first bus and second bus or to either said first bus or second bus, responsive to the shifting operation and direction to be applied to said data to be processed;
• a first data compensating circuit capable of compensating to make all bits of the data on said first bus "0", or to expand to a same value as a highest bit;
• a second data compensating circuit capable of compensating to make all bits of the data on said second bus "0";
• a decoder which includes n+1 numbers of control signal line connected to said MOS transistor array, and decodes a signal indicating a shift quantity and a shift direction of the shifting operation to be applied to said data to be processed, to signify one corresponding control signal line among said control signal lines, and to produce a signal indicating compensation of data done by said first data compensating circuit and second data compensating circuit;
• and
• an output bus for outputting n-bit data to the outside;
• wherein said MOS transistor array is so constructed that,
• MOS transistors are arranged in a matrix of n rows X n+1 columns,
• all bit lines of said first bus and all bit lines of said second bus are connected to sources of the MOS transistors in a step-like fashion,
• corresponding bit lines of said output bus are commonly connected to the sources of n+1 numbers of MOS transistor in respective lines, and
• corresponding control signal lines of said decoder are commonly connected to gates of n numbers of MOS transistor in respective columns.