Computer logic simulation with dynamic modeling

#A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office file or records, but otherwise reserves all copyright rights whatsoever.

#This invention relates to the field of computer logic simulation.

#Techniques are known for simulating the operation of a proposed logic design. One such technique is incorporated into the computer simulation software sold under the trademark MAX-PLUS available from Altera Corporation of San Jose, Calif. With reference to FIG. 1, a typical computer logic simulation technique proceeds by initially providing a logic design in the form of a schematic or netlist stored in a file (10) and converting the netlist by means of a logic compiler (12) into a simulator logic netlist (14) that is used by a logic simulator (15). A set of simulation input vectors (16) is also provided to the logic simulator (15), which reads the simulator logic netlist (14) along with the simulated input vectors (16) and "simulates" the operation of the logic design by propagating logic levels through the logic primitives in order to generate a set of output vectors (18), which are the simulated outputs of the logic design. This process has been found to be exceedingly useful in the field of logic design, particularly for complex circuits. However, this process can be very time consuming (particularly for complex circuits), since the simulator must continually interpret a very large netlist as it propagates the logic levels of the design.

#FIG. 1 is a schematic diagram showing a prior art computer logic simulator system;

#FIG. 2 is a schematic diagram illustrating a computer logic simulation system incorporating the invention;

#FIG. 3 is a flow chart illustrating the invention;

#Turning now to the drawings, as has already been described, FIG. 1 illustrates a prior art computer logic simulation system. In this Figure, elements depicted with rectangular geometry, such as the logic compiler (12) and simulator (15) represent executable programs, while elements depicted with cylindrical geometry, such as elements 10, 14, 16 and 18, represent data files.

#With reference to FIG. 2, a system incorporating the invention employs elemental geometry identical to that used in FIG. 1, with identical reference numerals being applied to identical elements. Thus, the system shown in FIG. 2 includes a first file (10) containing the network list describing the logic design, a simulation input vector file (16), a simulator (15) and simulation output vector file (18). A logic compiler (20) examines the network list contained in the logic design file (10) and converts the network list of some portions into a section of executable code whose function is a "black box" that simulates that portion. The executable code forms a dynamic model file (21). Logic compiler (20) converts the netlist of the remaining portions of the network list stored in logic design file (10) into a simulator logic network list which is stored in a file (22). During simulation, input vectors are read by simulator (15), along with the contents of the simulator logic netlist file (22). When the simulator needs to simulate those portions of the original network list which were converted into executable code, the simulator simply executes the code in the dynamic model file (21) corresponding to that portion. Because execution of the code is a very fast operation compared to the interpretive operation which must be performed on the simulator logic network list, the speed of the simulation process is substantially increased, with the result that the process can be completed in a substantially shorter time period. In addition, the size of the simulator logic network list is significantly reduced due to the substitution of the executable code for selected portions of the original network list.

#FIG. 3 illustrates the overall operation of the method of the invention. As seen in this Fig., the logic compiler first creates a fully expanded simulation network list from the original network list contained in the logic design file (10). Next, all "keeper" nodes are identified. A "keeper" node is a node whose removal is prohibited for one of three reasons: (a) the node does not feed any device; (b) the node feeds a device which cannot be traced through (as described more fully below); and (c) the node has a name whose removal is prohibited. Once all "keeper" nodes have been identified, each "keeper" node is processed by the logic compiler (20) to determine whether any network feeding a keeper node is eligible to be reduced to a dynamic device model (DDM) in the form of executable code. This eligibility test is conducted by tracing through the network associated to the keeper node back to all sources, eliminating any networks having devices which embody a cyclic function, and comparing the number of devices encountered in the network with a threshold value (3 in the preferred embodiment). If the network is deemed worthwhile for replacement, the network list is subjected to a further tracing process in the course of which a decision diagram is generated in the manner described below. After completion of the decision diagram, a compiled code is generated for the dynamic device model and inserted into the simulator logic netlist file (22). If the network is deemed not worthy of replacement, it is stored in the ordinary way in the simulator logic netlist file (22). After all "keeper" nodes have been thus processed, the system is now prepared to conduct the computer logic simulation process with the simulation input vectors.