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US 5,477,466 AGranted
Method and structure for improving patterning design for processing
AssigneeLSI Logic Corporation
InventorsPrabhakar P. Tripathi, Bruce Whitefield, Chi-Hung Wang
Life of this patent
Estimating the term…
Abstract
A method of interactive feedback in semiconductor processing is provided which compensates for lithographic proximity effects, reactive ion etch loading effects, electromigration and stress due to layering.
Claims18
A method of fabricating an integrated circuit, comprising the steps of:
- (a) generating a circuit layout of said integrated circuit, comprising the substeps of:
- (a1) determining a surface area of metallization used in said circuit layout;
- (a2) comparing said surface area with a first predetermined value;
- (a3) determining a distance between a first working line and a second working line to determine if said first or said second working line is a lonely line;
- (a4) comparing said distance to a second predetermined value;
- and
- if said distance is greater than said second predetermined value,
- (a5) placing a dummy line at a predetermined distance from said lonely line;
- (b) forming active regions on an integrated circuit chip;
- (c) forming a metallization layer on the chip;
- (d) forming a photoresist layer on the metallization layer;
- (e) imaging the photoresist layer in accordance with said circuit layout;
- (f) developing the photoresist layer;
- (g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask;
- and
- (h) removing the photoresist layer.
13 more elements
A method of fabricating an integrated circuit, comprising the steps of:
- (a) generating a circuit layout using a computer, comprising the substeps of:
- (a1) determining a surface area of said metallization;
- (a2) comparing said area with a first predetermined value;
- if said area is less than said first predetermined value, said computer proceeding with the following series of substeps;
- (a3) initializing a mesh pattern of local wires with physical wires;
- (a4) removing an overlap between said local and said physical wires;
- (a5) removing portions of said local wires which are within a first predetermined distance from said physical wires;
- (a6) removing segments of said local wires of a length less than a second predetermined value;
- (a7) creating a boundary of a second predetermined distance surrounding said physical wires;
- and
- (a8) removing segments of said local wires which are outside said boundary;
- (b) forming active regions on an integrated circuit chip;
- (c) forming a metallization layer on the chip;
- (d) forming a photoresist layer on the metallization layer;
- (e) imaging the photoresist layer in accordance with said circuit layout;
- (f) developing the photoresist layer;
- (g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask;
- and
- (h) removing the photoresist layer.
16 more elements
A method of fabricating an integrated circuit, comprising the steps of:
- (a) generating a circuit layout of said integrated circuit, comprising the substeps of:
- (a1) determining a surface area of a layer of metallization used in said circuit;
- (a2) comparing said surface area with a first predetermined value;
- if said area is less than said first predetermined value, proceeding with the following series of steps;
- (a3) initializing a mesh pattern of local wires with physical wires;
- (a4) removing an overlap between said local and said physical wires;
- (a5) removing portions of said local wires which are within a first predetermined distance from said physical wires;
- (a6) removing segments of said local wires of a length less than a second predetermined value;
- (a7) creating a boundary of a second predetermined distance surrounding said physical wires;
- and
- (a8) removing segments of said local wires which are outside said boundary;
- (b) forming active regions on an integrated circuit chip;
- (c) forming a metallization layer on the chip;
- (d) forming a photoresist layer on the metallization layer;
- (e) imaging the photoresist layer in accordance with said circuit layout;
- (f) developing the photoresist layer;
- (g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask;
- and
- (h) removing the photoresist layer.
16 more elements
A method of forming metallization on an integrated circuit, comprising the steps of:
- (a) generating a circuit layout of said integrated circuit, comprising the substeps of:
- (a1) determining a surface area of metallization used in said circuit layout;
- (a2) comparing said surface area with a first predetermined value;
- (a3) determining a distance between a first working line and a second working line to determine if said first or said second working line is a lonely line;
- (a4) comparing said distance to a second predetermined value;
- and
- if said distance is greater than said second predetermined value,
- (a5) placing a dummy line at a predetermined distance from said lonely line;
- (b) forming a metallization layer on an integrated circuit chip;
- (c) forming a photoresist layer on the metallization layer;
- (d) imaging the photoresist layer in accordance with said circuit layout;
- (e) developing the photoresist layer;
- (f) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask;
- and
- (g) removing the photoresist layer.
12 more elements
A method of forming metallization on an integrated circuit, comprising the steps of:
- (a) generating a circuit layout using a computer, comprising the substeps of:
- (a1) determining a surface area of said metallization;
- (a2) comparing said area with a first predetermined value;
- if said area is less than said first predetermined value, said computer proceeding with the following series of substeps;
- (a3) initializing a mesh pattern of local wires with physical wires;
- (a4) removing an overlap between said local and said physical wires;
- (a5) removing portions of said local wires which are within a first predetermined distance from said physical wires;
- (a6) removing segments of said local wires of a length less than a second predetermined value;
- (a7) creating a boundary of a second predetermined distance surrounding said physical wires;
- and
- (a8) removing segments of said local wires which are outside said boundary;
- (b) forming a metallization layer on an integrated circuit chip;
- (d) forming a photoresist layer on the metallization layer;
- (e) imaging the photoresist layer in accordance with said circuit layout;
- (f) developing the photoresist layer;
- (g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask;
- and
- (h) removing the photoresist layer.
15 more elements
A method of forming metallization on an integrated circuit, comprising the steps of:
- (a) generating a circuit layout of said integrated circuit, comprising the substeps of:
- (a1) determining a surface area of a layer of metallization used in said circuit;
- (a2) comparing said surface area with a first predetermined value;
- if said area is less than said first predetermined value, proceeding with the following series of steps;
- (a3) initializing a mesh pattern of local wires with physical wires;
- (a4) removing an overlap between said local and said physical wires;
- (a5) removing portions of said local wires which are within a first predetermined distance from said physical wires;
- (a6) removing segments of said local wires of a length less than a second predetermined value;
- (a7) creating a boundary of a second predetermined distance surrounding said physical wires;
- and
- (a8) removing segments of said local wires which are outside said boundary;
- (b) forming a metallization layer over the chip;
- (c) forming a photoresist layer over the metallization layer;
- (d) imaging the photoresist layer in accordance with said circuit layout;
- (e) developing the photoresist layer;
- (f) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask;
- and
- (g) removing the photoresist layer.
15 more elements
Dependencies are inferred from the claim text.