Delay circuit for delaying differential signals includes separately controllable first and second load and clamp circuits for effecting different delay times

A cascade of delay circuits, each of said delay circuits being suitable for delaying differential signals, each of said delay circuits comprising a first input and a second input, a first output and a second output, a first current source, a first switching transistor and a second switching transistor each comprising a control electrode and a first main electrode and a second main electrode, the first input and the second input of the delay circuit being coupled to the control electrodes of the first switching transistor and the second switching transistor, respectively, the first main electrodes of the first switching transistor and the second switching transistor being coupled to one another and, via the first current source, to a first power supply terminal, the second main electrodes of the first switching transistor and the second switching transistor being coupled to the first output and the second output, respectively, of the delay circuit, each delay circuit further comprising first load circuits for coupling, respectively, the first output and the second output to a second power supply terminal, and respective first clamp circuits coupled to the first output and the second output for limiting differences between a voltage on the second power supply terminal and voltages on the first output and the second output, characterized in that each delay circuit comprises a second current source, second load circuits, second clamp circuits, and switching means for selectively connecting the second current source, the second load circuits and the second clamp circuits in parallel with the first current source, the first load circuits, and the first clamp circuits, respectively.