US 5,477,181 A · Programmable multiphase clock divider

Abstract

A programmable multiphase clock divider for selectively frequency dividing a multiphase input clock to provide a lower-frequency, self-aligned, multiphase output clock includes a counter, combinational logic circuitry, a multiphase signal generator and a multiplexor. With the counter serving as the sole frequency divider element, multiple phase-aligned clock phases are generated which are then programmably multiplexed to provide the desired frequency-divided, self-aligned clock phases. The counter, in response to a preset signal and an input clock phase, generates a multibit count signal, one bit of which forms the first output clock phase. The combinational logic circuitry receives a programming signal for decoding the multibit count signal to generate the counter preset signal and an output control signal. The multiphase signal generator successively latches the first output clock phase with the aforementioned input clock phase and additional input clock phases to generate a number of synchronous, intermediate clock phases. The multiplexor, in response to the output control signal, multiplexes the intermediate clock phases to provide further output clock phases. All of the output clock phases are phase-aligned with one another and are at a lower frequency than that of the input clock phase. Multiple ones of such clock dividers can be programmed to frequency divide by selected prime numbers and cascaded to achieve virtually any desired frequency division ratio while maintaining self-aligned output clock phases.

Claims21

Dependent claims

A programmable multiphase clock divider for selectively frequency dividing a multiphase input clock to provide a lower-frequency, self-aligned, multiphase output clock, said clock divider comprising:

a frequency divider for receiving a first input clock phase at an input frequency and a programming signal and in accordance therewith providing a first output clock phase at an output frequency and an output control signal, wherein said output frequency is lower than said input frequency;
and
a clock generator, coupled to said frequency divider, for receiving said first input clock phase, said first output clock phase, said output control signal and a plurality of additional input clock phases at said input frequency and in accordance therewith providing a plurality of additional output clock phases at said output frequency, wherein said first input clock phase and said plurality of additional input clock phases together form a plurality of noncoincident input clock signals with a plurality of predetermined relative phase relationships between temporally adjacent ones thereof, and wherein said first output clock phase and said plurality of additional output clock phases together form a plurality of noncoincident output clock signals with each one thereof corresponding to a respective one of said plurality of noncoincident input clock signals, and further wherein said plurality of predetermined relative phase relationships is maintained between corresponding, temporally adjacent ones of said plurality of noncoincident output clock signals.

A method of providing a programmable multiphase clock divider for selectively frequency dividing a multiphase input clock to provide a lower-frequency, self-aligned, multiphase output clock, said method comprising the steps of:

providing a frequency divider for receiving a first input clock phase at an input frequency and a programming signal and in accordance therewith providing a first output clock phase at an output frequency and an output control signal, wherein said output frequency is lower than said input frequency;
and
providing a clock generator, for coupling to said frequency divider, for receiving said first input clock phase, said first output clock phase, said output control signal and a plurality of additional input clock phases at said input frequency and in accordance therewith providing a plurality of additional output clock phases at said output frequency, wherein said first input clock phase and said plurality of additional input clock phases together form a plurality of noncoincident input clock signals with a plurality of predetermined relative phase relationships between temporally adjacent ones thereof, and wherein said first output clock phase and said plurality of additional output clock phases together form a plurality of noncoincident output clock signals with each one thereof corresponding to a respective one of said plurality of noncoincident input clock signals, and further wherein said plurality of predetermined relative phase relationships is maintained between corresponding, temporally adjacent ones of said plurality of noncoincident Output clock signals.

A method for programmably frequency dividing a multiphase input clock to provide a lower-frequency, self-aligned, multiphase output clock, said method comprising the steps of:

receiving a plurality of input clock phases at an input frequency;
receiving a programming signal;
providing a first output clock phase at an output frequency in accordance with said programming signal and one of said plurality of input clock phases, wherein said output frequency is lower than said input frequency;
providing an output control signal in accordance with said programming signal;
and
providing a plurality of additional output clock phases at said output frequency in accordance with said first output clock phase, said output control signal and said plurality of input clock phases, wherein said first input clock phase and said plurality of additional input clock phases together form a plurality of noncoincident input clock signals with a plurality of predetermined relative phase relationships between temporally adjacent ones thereof, and wherein said first output clock phase and said plurality of additional output clock phases together form a plurality of noncoincident output clock signals with each one thereof corresponding to a respective one of said plurality of noncoincident input clock signals and further wherein said plurality of predetermined relative phase relationships is maintained between corresponding, temporally adjacent ones of said plurality of noncoincident output clock signals.

3 more elements

Dependencies are inferred from the claim text.

Programmable multiphase clock divider

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Programmable multiphase clock divider

Life of this patent

Abstract

Claims21