Ultra low power gain circuit (UGC)

An amplifier circuit, comprising:

• a transistor device having a source terminal, a drain terminal, and a gate terminal;
• an input capacitance Cin having a node coupled to said gate terminal;
• an output capacitance Cout having a node coupled to said source terminal;
• reset switch means for selectively coupling and uncoupling said node of said output capacitance to a predetermined reset potential;
• applying means, coupled to said drain terminal, for selectively applying a first predetermined potential to said drain terminal followed by a second predetermined potential, said applying means applying said first predetermined potential during a time that said reset switch means has uncoupled said node of said output capacitance from said reset potential, the application of said first predetermined potential causing said output capacitance to charge to a potential that is approximately equal to the first predetermined potential, the application of said second predetermined potential causing said output capacitance to begin discharging through said transistor device;
• and
• a capacitance (Cgs) coupled between said source terminal and said gate terminal, said Cgs capacitance coupling to said gate terminal a change in the potential that occurs at said output capacitance due to said applying means applying said second predetermined potential to said drain terminal,
• wherein a closed loop gain Acl of said transistor is given by:
• ##EQU4##

A method of operating an amplifier circuit, comprising the steps of:

• providing an amplifier circuit that includes a transistor device having a source terminal, a drain terminal, a gate terminal, and a capacitance Cgs that is coupled between the gate terminal and the source terminal, the amplifier circuit further including an input capacitance Cin having a node coupled to the gate terminal and an output capacitance Cout having a node coupled to the source terminal;
• during a first time period,
• coupling the node of Cin to an input voltage potential while coupling the node of Cout to a reset voltage potential;
• during a second time period,
• storing the input voltage potential on the node of Cin by uncoupling the node of Cin from the input voltage potential;
• uncoupling the node of Cout from the reset voltage potential;
• and
• coupling the drain of the transistor device to a first voltage potential and charging the node of Cout to approximately the first voltage potential;
• during a third time period,
• coupling the drain of the transistor device to a second voltage potential and beginning the discharging Cout to the second voltage potential while also capacitively coupling to the gate terminal, through Cgs, a change in potential due to the discharging of Cout, the voltage potential at the gate terminal continuing to change until a difference in potential between the gate terminal and the source terminal is less than a threshold voltage of the transistor;
• and
• terminating the discharging of Cout by turning off the transistor when the difference in voltage potential between the gate terminal and the source terminal is less than the threshold voltage of the transistor, whereby a voltage potential then appearing at the node of Cout is a function of the voltage potential then appearing at the gate terminal.