Finite state machine with means for the reduction of noise effects
AssigneeU.S. Philips Corporation
InventorsAloysius P. Thijssen, Franciscus G. M. Bouwman, Hendrik A. Vink
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Abstract
A finite state machine that may receive actuator signals and has a plurality of elementary sequential logic elements fed by the actuator signals. Through various interconnections between the elements a first set of interconnected logic states is realized that are activated through combined occurrence of a particular predecessor state and an associated actuator signal. In various ones of said logic states a particular output signal is produced. Furthermore, the finite state machine has a subset of redundant logic states that are aggregated together with a particular operational by appropriate interconnections for collectively emulating the operational state in question.
Claims12
A finite state machine having noise effect reduction, comprising:
- an actuator signal input;
- a plurality of sequential logic elements fed by said actuator signal input and being interconnected to realize a first set of interconnected logic states, each interconnection linking a predecessor state and a respective logic state, each respective logic state being selectively activated through combined occurrence of a respective predecessor state and an associated actuator signal received from said actuator signal input;
- a signal output fed by said logic elements, being under control of each member of at least a first subset of said logic states and outputting an output signal related to said first subset;
- and
- at least one second subset of logic states,
- the member states of said at least one second subset being mutually equivalent with a particular state of said first subset linked by logical interconnections connecting all member states of said second subset and said particular state, collectively emulating a function of said particular state within said first subset.
A finite state machine having an input, comprising:
- a plurality of machine states, a tint subset of said machine states being obtainable by providing selected data sequences at the input, each member state of said first subset being related to a respective succeeding state, and a second subset of said machine states not being obtainable through providing said selected data sequences at the input;
- and
- a logical processor for detecting the occurrence of a member state of said second subset upon input of any of said selected data sequences, and upon detection, emulating a particular member state of said first subset to provide an equivalent respective succeeding state to that related to said particular member state.
Dependencies are inferred from the claim text.