Programmable output device with integrated circuit

#The present invention pertains in general to multiplexing the function of the output pins on an integrated circuit and, more particularly, to utilizing the output pins of an integrated circuit to both drive an external device and also receive programming inputs thereon.

#Due to the increasing density of integrated circuits and the increasing number of functions that are integrated into the integrated circuit, each pin associated with a packaged device is utilized to serve multiple functions. For example, some integrated circuits are operated in a test mode or in an operating mode. In the test mode, the operating mode is disabled and signals input thereto are then recognized as being test signals. Typically, one pin is dedicated to selecting the test mode or the operating mode. Thereafter, input pins can typically serve two different input functions. When the pins are used in programming applications with three-state inputs, typically small impedances are utilized. For example, the pin is allowed to float or be connected directly to the positive or negative rail.

#Although output driver pins have been utilized for input/output functions, these functions are typically separate operations, i.e., the output device is driven by the pin, and an output function is typically not present when an input signal is applied thereto. This is due to the fact that the impedance presented to the pin by the output device interferes with the input function. Further, the input function typically also requires a low impedance. For example, if an input required a low logic state signal to be applied thereto, the signal could not be applied thereto while the active device was attached, as this may cause excessive current to flow through the active device and may, in fact, turn the active device on if it were some device such as a display element.

#For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying Drawings in which:

#FIG. 1 illustrates an overall block diagram of the integrated circuit and associated output driven devices, with the programming resistors attached to the output drive/program pins;

#FIG. 2 illustrates a detail of a logic diagram for the programmable output drive/program pins;

#Referring now to FIG. 1, there is illustrated an overall block diagram of an integrated circuit 10 utilizing the programmable output pins in accordance with one aspect of the present invention. The programmable IC 10 has a plurality of output lines 12 associated with a separate group of output drive/program pins. In the illustrated example of FIG. 1, the output driver lines 12 are input to an LED output device 14, which output device 14 is an LED display. The LED output device 14 has an Enable High line 16 connected thereto which is output from one pin of the programmable IC 10.

#Each of the output lines 12 is operable to have a programming resistor 18 associated therewith. Each of the resistors 18 is connected to a switch 20. The switch 20 is operable to be connected to one of three states, either to a ground line 22, a V.sub.cc line 24 or a floating node 26. Although the switch 20 is illustrated, it should be understood that, in the preferred embodiment, the resistor is either tied to ground, tied to V.sub.cc or left out of the circuit. Therefore, a resistor will be disposed on the output line that will either be a pull up resistor, a pull down resistor, or no resistor. The resistor 18 has a value of approximately 500 KOhms. By placing the resistors 18 on the appropriate one of the lines 12, the line can be programmed with three separate states, high, low and floating.

#Referring now to FIG. 2, there is illustrated a detailed block diagram of the driver portion of the programmable IC 10. A plurality of output drive/program pads 30 are provided, one associated with each of the driver lines 12. Additionally, an enable pin 32 is provided which is connected to the Enable High line 16. Each of the output drive/program pads 30 is connected to a node 36. Each of the nodes 36 is operable to be connected to the output of a pad driver 38 or to the input of a program buffer 40. Each of the program buffers 40 is controlled by a program bias circuit 42, which program bias circuit 42 is operable to turn on each of the program buffers 40 and also receive control signals from a central processing unit (CPU) 46 through control lines 48. The CPU is also operable to input control lines on a line 49 to each of the program buffers 40. The outputs of each of the program .! buffers 40 are connected to one of a group of lines 50, which lines 50 are input to the register 52. Therefore, the outputs of the program buffers 40 are latched into a register 52, which can be read by the CPU 46 through a bus 54. The register 52 in effect appears as a dual port RAM. The CPU 46 is also operable to output the control signals to activate and control the drivers 38. The control signals are input on input lines 56 to the inputs of the drivers 38.