US 5,477,165 A · Programmable logic module and architecture for field programmable gate array device

Abstract

A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

Claims70

Dependent claims

A combinatorial logic unit comprising:

a cascaded multiplexer architecture having a plurality of multiplexer planes, each of said multiplexer planes including at least one multiplexer having inputs, at least one control input connected to at least one input node and at least one output;
at least one multiplexer in a first of said multiplexer planes having said inputs connected to input nodes;
inputs of said at least one multiplexer in said multiplexer planes succeeding said first multiplexer plane connected to said outputs of said at least one multiplexer in preceding multiplexer planes in said cascaded multiplexer architecture;
at least one multiplexer in a last of said multiplexer planes having said at least one output connected to an output conductor;
and
at least one inverter having an input connected to an input node and an output selectively connectable to individual ones of said input nodes by user-programmable interconnect elements.

3 more elements

A combinatorial logic unit comprising:

a first multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input connected to a third input node, and an output;
a second multiplexer having a first input connected to a fourth input node, a second input connected to a fifth input node, a control input connected to said third input node, and an output;
a third multiplexer having a first input connected to a sixth input node, a second input connected to a seventh input node, a control input connected to said third input node, and an output;
a fourth multiplexer having a first input connected to a eighth input node, a second input connected to a ninth input node, a control input connected to said third input node, and an output;
a fifth multiplexer having a first input connected to the output of said first multiplexer, a second input connected to the output of said second multiplexer, a control input connected to a tenth input node, and an output;
a sixth multiplexer having a first input connected to the output of said third multiplexer, a second input connected to the output of said fourth multiplexer, a control input connected to said tenth input node, and an output;
a seventh multiplexer having a first input connected to the output of said fifth multiplexer, a second input connected to the output of said sixth multiplexer, a control input connected to an eleventh input node, and an output connected to an output conductor;
a plurality of interconnect conductors intersecting said input nodes of said first, second, third and fourth multiplexers, said plurality of interconnect conductors selectively connectable to individual ones of said input nodes by user programmable interconnect elements;
and
an inverter having an input connected to one of said interconnect conductors and an output selectively connectable to individual ones of said input nodes of said first, second, third and fourth multiplexers by user-programmable interconnect elements.

7 more elements

A combinatorial logic unit comprising:

a first multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input connected to a third input node, and an output;
a second multiplexer having a first input connected to a fourth input node, a second input connected to a fifth input node, a control input connected to said third input node, and an output;
a third multiplexer having a first input connected to a sixth input node, a second input connected to a seventh input node, a control input connected to said third input node, and an output;
a fourth multiplexer having a first input connected to a eighth input node, a second input connected to a ninth input node, a control input connected to said third input node, and an output;
a fifth multiplexer having a first input connected to the output of said first multiplexer, a second input connected to the output of said second multiplexer, a control input connected to a tenth input node, and an output;
a sixth multiplexer having a first input connected to the output of said third multiplexer, a second input connected to the output of said fourth multiplexer, a control input connected to said tenth input node, and an output;
a seventh multiplexer having a first input connected to the output of said fifth multiplexer, a second input connected to the output of said sixth multiplexer, a control input connected to an eleventh input node, and an output;
an eighth multiplexer having a first input connected to a twelfth input node, a second input connected to a thirteenth input node, a control input connected to the output of said seventh multiplexer, and an output connected to an output conductor;
a plurality of interconnect conductors intersecting said input nodes of said first, second, third, fourth and eighth multiplexers, said plurality of interconnect conductors selectively connectable to individual ones of said input nodes by user programmable interconnect elements;
a first inverter having an input connected to one of said interconnect conductors and an output selectively connectable to individual ones of said input nodes of said first, second, third and fourth multiplexers by user-programmable interconnect elements;
and
a second inverter having an input connected to one of said interconnect conductors and an output selectively connectable to individual ones of said input nodes of said first, second, third and fourth multiplexers by user-programmable interconnect elements.

9 more elements

Dependencies are inferred from the claim text.

Programmable logic module and architecture for field programmable gate array device

Life of this patent

Programmable logic module and architecture for field programmable gate array device

Life of this patent

Abstract

Claims70