Capacitor and diode circuitry for on chip power spike detection

#This invention is in the field of integrated circuits and generally relates to memory devices and detection devices.

#Detection of conditions under which some information is apt to be lost can be of primary importance in the development of memory system such as those including static random access memories (SRAMs) or dynamic random access memories (DRAMs). Failure which causes a memory to store the wrong memory state may result, for instance, from the loss of memory power or from memory exposure over a period of time to accumulated radiation. Additionally, memory error may result from memory exposure to a pulse of gamma radiation (gamma dot).

#It is desirable to have a memory system capable of detecting conditions that lead to memory error such that recovery procedures can be instituted. Furthermore, it is desirable to have a memory system capable of detecting an impending error causing situation such that memory error can be prevented.

#FIG. 1 is a schematic drawing which illustrates a first preferred embodiment of the invention.

#FIG. 2 is a schematic drawing which illustrates a second preferred embodiment of the invention.

#FIG. 3 is a schematic drawing which illustrates a third preferred embodiments of the invention.

#The invention is used in connection with an associated memory array in order to detect the occurrence of a condition that is likely to cause error in the array or the high likelihood of impending error in the array.

#The invention uses a detection memory cell as a transient dose detector by introducing some asymmetry so that the cell has a favored state. On set (or re-set), a WRITE into the cell places the detection memory cell in an unfavored state. Under sufficient radiation effects or power down situations, the detection memory cell switches to the favored state.

#The asymmetry introduced to the cell must be such that the cell will change to the favored state at a transient dose level or accumulated radiation level that is approaching the level at which cells in the associated memory array may be upset or at which associated circuitry will fail. One way to do this is to introduce an asymmetry on the bit lines of the detector cell that matches the worst case asymmetry in the memory array, i.e. n-1 memory cells with a voltage state opposite to the set state of the detection memory cell, where n is the number of rows in the memory array. In addition to the cell loading, the bit lines should be loaded the same as in the actual memory array, for example, being held in precharge when the chip is not enabled.