Semiconductor IC device having a RAM interposed between different logic sections and by-pass signal lines extending over the RAM for mutually connecting the logic sections

A semiconductor integrated circuit device comprising:

• a semiconductor substrate having a main surface;
• a first logic circuit block and a separate, second logic circuit block being disposed on said main surface of said substrate, respectively, each of said first and second logic circuit blocks operating on internally provided signals to produce internal logic signals and including a plurality of logic gates;
• a RAM type memory mat and a peripheral circuit thereof being provided on said main surface between said first and second logic circuit blocks, said RAM type memory mat including a plurality of memory cells, a plurality of first signal lines of a first level wiring layer and a plurality of second signal lines of a second level wiring layer, said second level wiring layer being arranged at a relatively higher level, of a multi-layer wiring arrangement, than said first level wiring layer with respect to the main surface of said semiconductor substrate, and said first and second signal lines being disposed in a coupling arrangement so that each memory cell is coupled to a first signal line and a second signal line;
• and
• a plurality of third signal lines of a third level wiring layer, for connecting said first logic circuit block with said second logic circuit block, being disposed over said main surface, said third level wiring layer being arranged at a higher level wiring layer than said second level wiring layer with respect to the main surface of said semiconductor substrate,
• wherein said third signal lines and said second signal lines are disposed to intersect each other, with respect to a plan view, at substantially right angles over said RAM type memory mat, and wherein said third signal lines are extended in a substantially straight-line form over said RAM type memory mat.