Microprocessor implementing single-step or sequential microcode execution while in test mode

A microprocessor comprising:

• a memory for storing a microprogram routine specifying a plurality of operations for executing a macroinstruction, said microprogram routine including a plurality of microinstructions each including a microsequence specifying bit pattern, and further including a last microinstruction in said microprogram routine including a finish microsequence specifying bit pattern;
• means, including a control output, for storing a control part of a first macroinstruction, the control part having either a first value indicating that said first macroinstruction is not a step-execution instruction or a second value indicating that said first macroinstruction is a step-execution instruction;
• a microsequencer, having an input for receiving a microsequence specifying bit pattern, for determining an address of a next microinstruction in said microprogram routine if a received microsequence specifying bit pattern is not said finish microsequence specifying bit pattern and for terminating said microprogram routine in response to a received finish microsequence specifying bit pattern;
• a microsequence specifying bit pattern storage means, having an input coupled to said memory, for storing a microsequence specifying bit pattern included in a microinstruction output from said memory;
• and
• a microsequence changing unit, having a control input coupled to said control output to receive a stored control part of said first macroinstruction, a sequence input coupled to receive said microsequence specifying bit pattern from said microsequence specifying bit pattern storage means and a sequence output coupled to the input of said microsequencer, for providing said microsequence specifying bit pattern stored by said microsequence specifying bit pattern storage means to said microsequencer when said stored control part has said first value and for compulsorily converting a received microsequence specifying bit pattern to a converted microsequence bit pattern equal to said finish microsequence specifying bit pattern, irrespective of whether said received microsequence specifying bit pattern is said finish microsequence specifying bit pattern, and providing said converted microsequence specifying bit pattern to said microsequencer when said stored control part has said second value to force termination of the microprogram routine.