Memory control device with vector processors and a scalar processor

A memory control system, including a main memory, a scalar processing unit and at least one vector processing unit, for data processing, the system comprising:

• a buffer memory for reading-out and writing-in a copy of an information block included in the main memory;
• a buffer address array, coupled to the main memory, for storing therein a store address of the main memory which corresponds to the copy of the information block stored in the buffer memory;
• first detector means, coupled to the buffer address array, for detecting whether the store address of data is held in the buffer address array when the scalar processing unit stores the data in the main memory;
• a front address array, coupled to the main memory, for storing therein a copy of contents of the buffer address array;
• second detector means, coupled to the front address array, for detecting whether the store address of data is held in the front address array when the at least one vector processing unit stores the data in the main memory;
• means for invalidating block information in the buffer memory, the block information included in that information which is written into the main memory by the at least one vector processing unit;
• a block valid memory, having a plurality of valid bits, each valid bit corresponding to one of a plurality of blocks into which the main storage is divided and which contain the block information, and each valid bit indicating whether a copy of a corresponding information block is stored in the buffer memory wherein each valid bit is provided for a different one of the plurality of blocks;
• means responsive to the writing of information into a selected block of the main memory by the at least one vector processing unit for reading a valid bit corresponding to the selected block from the block valid memory;
• and,
• means for accessing the block valid memory by the at least one vector processing unit prior to accessing the front address array, so as to allow access to said front address array when the corresponding valid bit in the block valid memory is valid, but preclude access to said front address array when the corresponding valid bit in the block valid memory is invalid.

A memory control system, including a main memory, a plurality of scalar processing units, and at least one vector processing unit, the system comprising:

• each scalar processing unit including a buffer memory for storing a copy of information of the main memory, a buffer address array for holding a store address of the information of which the copy is stored in the buffer memory, and first detector means for detecting whether the store address of data is held in the buffer address array when the scalar processing unit stores data in the main memory;
• a plurality of front address arrays, each assigned to one of the scalar processing units respectively for storing a copy of contents of a one buffer address array contained in the one scalar processing unit;
• a plurality of second detector means, coupled to the plurality of front address arrays respectively, for detecting whether the store address of data is held in the plurality of front address arrays when the at least one vector processing unit stores data in the main memory;
• a plurality of means, coupled to the plurality of second detector means respectively, for invalidating a block information in a corresponding buffer memory, the block information included in that information which is written into the main memory by the at least one vector processing unit;
• a block valid memory, common to the plurality of scalar processing units, having a plurality of valid bits each corresponding to one of a plurality of blocks into which the main memory is divided and which contains block information, each valid bit indicating whether a copy of a corresponding information block is stored in the buffer memory wherein each valid bit is provided for a different one of the plurality of blocks;
• means responsive to the writing of information into a selected block of the main memory by the at least one vector processing unit for reading a valid bit corresponding to the selected block that is positive from the block valid memory prior to accessing any of the plurality of front address arrays wherein the plurality of front address arrays need not be referenced if the valid bit is negative;
• and
• means for activating all of the second detection means only when the read-out valid bit represents positive.

A multi-processor system including scalar processors and vector processors, the system comprising:

• a main storage comprising a plurality of block groups, each block group comprising a plurality of blocks;
• a buffer storage means, corresponding to each scalar processor, for storing therein at least one of the plurality of blocks concurrently with the main storage;
• a vector processor request means for requesting a store operation to a selected block of a selected block group from a vector processor to the main storage;
• a block group valid table corresponding to the vector processor request means for storing group information representing the plurality of block groups of the main storage and indicating whether any block of the selected block group is stored in the buffer storage means;
• a block valid memory for storing block information representing the plurality of blocks of the main storage and indicating whether the selected block is stored in the buffer storage means;
• and,
• detection means for detecting whether the group information indicates that any block of the selected block group is stored in the buffer storage means and whether the block information indicates that the selected block is stored in the buffer storage means so that if the detection means detects that the selected block is not stored in the buffer storage means, then the buffer storage means can be by-passed during the store operation thereby increasing processing efficiency.

A method for effecting matching control between a main storage and a buffer storage in a multi-processor system including the main storage comprising block groups, each block group comprising blocks, a scalar processor including the buffer storage and a buffer address array, a front address array which stores information of the buffer address array, a block valid memory which stores information indicating whether a block of the main storage is also stored in the buffer storage, a block valid group table which stores information indicating whether any block of a block group is stored in the buffer storage, a vector processor, a first detector, and a second detector, the method comprising steps of:

• requesting a store operation to a store address location in a selected block of a selected block group from the vector processor to the main storage by the vector processor;
• first detecting, by the first detector, whether any block of the selected block group is stored in the buffer storage;
• second detecting, by the second detector, whether the selected block of the selected block group is stored in the buffer storage if the first detector detects that any block of the selected block group is stored in the buffer storage;
• accessing the front address array to determine whether a content of the store address location is present in the buffer storage, the accessing occurring only if the first and second detecting make positive determinations;
• and;
• performing the store operation to the main storage and invalidating the selected block in the buffer storage in accordance with the positive determinations of the first detecting and the second detecting that the selected block is stored in the buffer storage and a determination of the accessing of the front address array that the content of the store address location is present in the buffer storage.