Supervisory control method and power saving control unit for computer system

A power saving control unit for a computer system, comprising:

• means a for switching a CPU of said computer system between a normal mode of ordinary power consumption and a power saving mode of small power consumption;
• means B whereby addresses accessed by said CPU in a predetermined period of time Tx are stored in an address memory, said stored addresses being defined as learned addresses;
• means C for checking immediately after the operation of said means B whether or not said CPU accesses an address other than said learned addresses in a predetermined period of time Ty related to said period of time Tx;
• means D for causing said means B and C to repeatedly perform their operation in the state wherein said CPU is in said normal mode of operation and said CPU is put in said power saving mode, if the condition is not met when no access of said CPU to an address other than said learned addresses is detected in said time Ty;
• means E for detecting an access of said CPU to an address other than said learned addresses when said CPU is in said power saving mode of operation;
• and
• means F for putting said CPU in said normal mode of operation when an access of said CPU to an address other than said learned addresses is detected by said means E.

A power saving control unit for a computer system including a CPU and a system bus, comprising:

• switching circuit for switching said CPU of said computer system between a normal mode of ordinary power consumption and a power saving mode of small power consumption;
• address memory and comparison circuit for storing addresses accessed by said CPU in a predetermined period of time in said address memory, and for checking whether or not said CPU accesses an address other than said stored addresses in another predetermined time;
• address detector for detecting an access of said CPU to an address other than said stored addresses when said CPU is in said power saving mode of operation;
• status judgement and power saving controller for supervising signals on said system bus and for putting said CPU in said normal mode of operation when an access of said CPU to an address other than said stored addresses is detected by said address memory and comparison circuit, whereby said address memory and comparison circuit and said address detector repeatedly perform their operation in the state wherein said CPU is in said normal mode of operation and said CPU is put in said power saving mode if the condition is not met when no access of a said CPU to an address other than said stored addresses is detected in said another predetermined period of time;
• high-speed clock generator for supplying a clock signal of higher frequency to said CPU through said switching circuit for the normal mode;
• and
• low-speed clock generator for supplying a clock signal of lower frequency to said CPU through said switching circuit for the power saving mode.